3.16.5. Debug port register summary

Table 3.208 shows the DP register summary, and summarizes which registers are implemented on a JTAG-DP and which are implemented on an SW-DP.

Table 3.208. Debug port register summary

ABORTYesYesAP Abort Register. See AP Abort register, ABORT.
IDCODEYesNoID Code Register. See Identification Code register, IDCODE.
DPIDRNoYesDebug Port Identification Register. See Debug Port Identification Register, DPIDR.
CTRL/STATYesYesControl/Status Register. See Control/Status register, CTRL/STAT.
SELECTYesYesAP Select Register. See AP Select register, SELECT.
RDBUFFYesYesRead Buffer Register. See Read Buffer register, RDBUFF.
DLCRNoYesData Link Control Register. See Data Link Control Register, DLCR (SW-DP only).
TARGETIDNoYesTarget Identification Register. See Target Identification register, TARGETID (SW-DP only).
DLPIDRNoYesData Link Protocol Identification Register. See Data Link Protocol Identification Register, DLPIDR (SW-DP only).
RESENDNoYesRead Resend Register. See Read Resend register, RESEND (SW-DP only).

JTAG-DP register summary

Table 3.209 shows all implemented registers accessible through the JTAG interface. All other Instruction Register (IR) instructions are implemented as BYPASS. An external TAP controller must be implemented in accordance with the ARM® Debug Interface Architecture Specification, ADIv5.0 to ADIv5.2, if more IR registers are required, for example, JTAG TAP boundary scan. See JTAP-DP register descriptions.

Table 3.209. JTAG-DP register summary

IR instruction valueJTAG-DP registerDR scan widthDescription
0b1000ABORT35JTAG-DP Abort Register, ABORT.
0b1010DPACC35JTAG DP/AP Access Registers, DPACC/APACC.
0b1110IDCODE32JTAG Device ID Code Register, IDCODE.
0b1111BYPASS1JTAG Bypass Register, BYPASS.

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