3.3.1. Debug Power Request register

The CPWRUPREQ register characteristics are:

Purpose

Controls the values of the cpwrupreq outputs from the GPR. Each bit in this register controls the corresponding output on the cpwrupreq port. GPR contains hardware logic to ensure that the 4-phase handshake is not violated on the CPWRUP interfaces.

When GPR asserts a powerup request that is not acknowledged, that is, cpwrupreq[n] = 1 and cpwrupack[n] = 0, writing a 0 to the CPWRUPREQ register bit[n] does not affect the cpwrupreq[n] output.

Similarly, when GPR sends a powerdown request that is not acknowledged, that is, cpwrupreq[n] is 0 and cpwrupack[n] = 1, writing a 1 to the CPWRUPREQ register bit[n] does not affect the cpwrupreq[n] output.

Usage constraints

There are no usage constraints.

Configurations

This register is available in all configurations.

Attributes

See the register summary in Table 3.1.

There is a one to one mapping between the register locations and the CPWRUPREQ bits.

Table 3.2 shows the bit assignments.

Table 3.2. CPWRUPREQ register bit assignments

BitsNameFunction
[31]CPWRUPREQBit31

Bit[31] of the cpwrupreq output port.

0

Drive 0 on cpwrupreq[31] output port.

1

Drive 1 on cpwrupreq[31] output port.

[30]CPWRUPREQBit30

Bit[30] of the cpwrupreq output port:

0

Drive 0 on cpwrupreq[30] output port.

1

Drive 1 on cpwrupreq[30] output port.

[29]CPWRUPREQBit29

Bit[29] of the cpwrupreq output port:

0

Drive 0 on cpwrupreq[29] output port.

1

Drive 1 on cpwrupreq[29] output port.

[28]CPWRUPREQBit28

Bit[28] of the cpwrupreq output port:

0

Drive 0 on cpwrupreq[28] output port.

1

Drive 1 on cpwrupreq[28] output port.

[27]CPWRUPREQBit27

Bit[27] of the cpwrupreq output port:

0

Drive 0 on cpwrupreq[27] output port.

1

Drive 1 on cpwrupreq[27] output port.

[26]CPWRUPREQBit26

Bit[26] of the cpwrupreq output port:

0

Drive 0 on cpwrupreq[26] output port.

1

Drive 1 on cpwrupreq[26] output port.

[25]CPWRUPREQBit25

Bit[25] of the cpwrupreq output port:

0

Drive 0 on cpwrupreq[25] output port.

1

Drive 1 on cpwrupreq[25] output port.

[24]CPWRUPREQBit24

Bit[24] of the cpwrupreq output port:

0

Drive 0 on cpwrupreq[24] output port.

1

Drive 1 on cpwrupreq[24] output port.

[23]CPWRUPREQBit23

Bit[23] of the cpwrupreq output port:

0

Drive 0 on cpwrupreq[23] output port.

1

Drive 1 on cpwrupreq[23] output port.

[22]CPWRUPREQBit22

Bit[22] of the cpwrupreq output port:

0

Drive 0 on cpwrupreq[22] output port.

1

Drive 1 on cpwrupreq[22] output port.

[21]CPWRUPREQBit21

Bit[21] of the cpwrupreq output port:

0

Drive 0 on cpwrupreq[21] output port.

1

Drive 1 on cpwrupreq[21] output port.

[20]CPWRUPREQBit20

Bit[20] of the cpwrupreq output port:

0

Drive 0 on cpwrupreq[20] output port.

1

Drive 1 on cpwrupreq[20] output port.

[19]CPWRUPREQBit19

Bit[19] of the cpwrupreq output port:

0

Drive 0 on cpwrupreq[19] output port.

1

Drive 1 on cpwrupreq[19] output port.

[18]CPWRUPREQBit18

Bit[18] of the cpwrupreq output port:

0

Drive 0 on cpwrupreq[18] output port.

1

Drive 1 on cpwrupreq[18] output port.

[17]CPWRUPREQBit17

Bit[17] of the cpwrupreq output port:

0

Drive 0 on cpwrupreq[17] output port.

1

Drive 1 on cpwrupreq[17] output port.

[16]CPWRUPREQBit16

Bit[16] of the cpwrupreq output port:

0

Drive 0 on cpwrupreq[16] output port.

1

Drive 1 on cpwrupreq[16] output port.

[15]CPWRUPREQBit15

Bit[15] of the cpwrupreq output port:

0

Drive 0 on cpwrupreq[15] output port.

1

Drive 1 on cpwrupreq[15] output port.

[14]CPWRUPREQBit14

Bit[14] of the cpwrupreq output port:

0

Drive 0 on cpwrupreq[14] output port.

1

Drive 1 on cpwrupreq[14] output port.

[13]CPWRUPREQBit13

Bit[13] of the cpwrupreq output port:

0

Drive 0 on cpwrupreq[13] output port.

1

Drive 1 on cpwrupreq[13] output port.

[12]CPWRUPREQBit12

Bit[12] of the cpwrupreq output port:

0

Drive 0 on cpwrupreq[12] output port.

1

Drive 1 on cpwrupreq[12] output port.

[11]CPWRUPREQBit11

Bit[11] of the cpwrupreq output port:

0

Drive 0 on cpwrupreq[11] output port.

1

Drive 1 on cpwrupreq[11] output port.

[10]CPWRUPREQBit10

Bit[10] of the cpwrupreq output port:

0

Drive 0 on cpwrupreq[10] output port.

1

Drive 1 on cpwrupreq[10] output port.

[9]CPWRUPREQBit9

Bit[9] of the cpwrupreq output port:

0

Drive 0 on cpwrupreq[9] output port.

1

Drive 1 on cpwrupreq[9] output port.

[8]CPWRUPREQBit8

Bit[8] of the cpwrupreq output port:

0

Drive 0 on cpwrupreq[8] output port.

1

Drive 1 on cpwrupreq[8] output port.

[7]CPWRUPREQBit7

Bit[7] of the cpwrupreq output port:

0

Drive 0 on cpwrupreq[7] output port.

1

Drive 1 on cpwrupreq[7] output port.

[6]CPWRUPREQBit6

Bit[6] of the cpwrupreq output port:

0

Drive 0 on cpwrupreq[6] output port.

1

Drive 1 on cpwrupreq[6] output port.

[5]CPWRUPREQBit5

Bit[5] of the cpwrupreq output port:

0

Drive 0 on cpwrupreq[5] output port.

1

Drive 1 on cpwrupreq[5] output port.

[4]CPWRUPREQBit4

Bit[4] of the cpwrupreq output port:

0

Drive 0 on cpwrupreq[4] output port.

1

Drive 1 on cpwrupreq[4] output port.

[3]CPWRUPREQBit3

Bit[3] of the cpwrupreq output port:

0

Drive 0 on cpwrupreq[3] output port.

1

Drive 1 on cpwrupreq[3] output port.

[2]CPWRUPREQBit2

Bit[2] of the cpwrupreq output port:

0

Drive 0 on cpwrupreq[2] output port.

1

Drive 1 on cpwrupreq[2] output port.

[1]CPWRUPREQBit1

Bit[1] of the cpwrupreq output port:

0

Drive 0 on cpwrupreq[1] output port.

1

Drive 1 on cpwrupreq[1] output port.

[0]CPWRUPREQBit0

Bit[0] of the cpwrupreq output port:

0

Drive 0 on cpwrupreq[0] output port.

1

Drive 1 on cpwrupreq[0] output port.


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