3.17.5. Debug port implementation-specific registers

This section describes the implementation-specific registers.

AP Abort register, ABORT

Purpose

Present in all debug port implementations. It forces a DAP abort on SW-DP. It also clears error and sticky flag conditions.

The AP Abort is always accessible, and returns an OK response if a valid transaction is received.

JTAG-DP

It is at address 0x0 when the IR contains ABORT.

SW-DP

It is at address 0x0 on write operations when the APnDP bit is equal to 0. Access to ABORT is not affected by the value of the CTRLSEL bit in the Select Register.

Attributes

Accesses to this register always complete on the first attempt.

Figure 3.213 shows the bit assignments.

Figure 3.213. JTAG-DP ABORT bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Figure 3.214 shows the bit assignments.

Figure 3.214. SW-DP ABORT bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 3.235 shows the bit assignments.

Table 3.235. ABORT register bit assignments

BitsFunctionDescription
[31:5]-Reserved, SBZ.
[4]ORUNERRCLR[a]Setting this bit to 1 sets the STICKYORUN overrun error flag[b] to 0.
[3]WDERRCLR[a]Setting this bit to 1 sets the WDATAERR write data error flag[b] to 0.
[2]STKERRCLR[a]Setting this bit to 1 sets the STICKYERR sticky error flag[b] to 0.
[1]STKCMPCLR[a]Setting this bit to 1 sets the STICKYCMP sticky compare flag[b] to 0.
[0]DAPABORT

Setting this bit to 1 generates a DAP abort, which in turn aborts the current AP transaction.

Note

Perform this only if the debugger has received WAIT responses over an extended period.

[a] Implemented on SW-DP only. On a JTAG-DP this bit is Reserved, SBZ.

[b] In the Control/Status Register, see Control/Status register, CTRL/STAT.


Identification Code register, IDCODE

Purpose

Provides identification information about the JTAG-AP. The IDCODE register is accessed through its own scan chain. The Identification Code Register is:

  • A RO Register.

  • Always accessible.

Attributes

Figure 3.215 shows the bit assignments.

Figure 3.215. Identification Code register bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 3.236 shows the bit assignments.

Table 3.236. Identification Code register bit assignments

BitsFunctionDescription
[31:28]Version

Version code, 0x5:

[27:12]PARTNO

Part Number for the debug port, 0xBA00.

[11:1]MANUFACTURER

JEDEC Manufacturer ID, an 11-bit JEDEC code that identifies the designer of the device. See JEDEC Manufacturer ID. Figure 3.215 shows the ARM value for this field as 0x23B. This value must not be changed.

[0]-Always 1.

JEDEC Manufacturer ID

This code is also described as the JEP-106 manufacturer identification code, and can be subdivided into two fields, as Table 3.237 shows. JEDEC codes are assigned by the JEDEC Solid State Technology Association, see JEP106M, Standard Manufactures Identification Code.

Table 3.237. JEDEC JEP-106 manufacturer ID code, with ARM values

JEP-106 fieldBits[a]ARM registered value
Continuation code4 bits, [11:8]0b0100, 0x4.
Identity code7 bits, [7:1]0b0111011, 0x3B.

[a] Field width, in bits, and the corresponding bits in the Identification Code Register.


Debug Port Identification Register, DPIDR

Purpose

Provides identification information about the SW-DP. It is at address 0b00 on read operations when the APnDP bit = 0. The value of the CTRLSEL bit in the SELECT register does not affect access to the DPIDR.

The Debug Port Identification Register is:

  • A RO Register.

  • Always accessible.

Attributes

Figure 3.215 shows the bit assignments.

Figure 3.216. Debug Port Identification register bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 3.236 shows the bit assignments.

Table 3.238. Debug Port Identification register bit assignments

BitsFunctionDescription
[31:28]REVISION

Revision code, 0x5

[27:20]PARTNO

Part Number for this debug port, 0xBA.

[19:17]-Reserved, SBZ.
[16]MINReads as 0, indicating that the Minimal Debug Port (MINDP) architecture is not implemented.
[15:12]VERSION0x2, indicating version 2 of the DP architecture is implemented.
[11:1]MANUFACTURER

JEDEC Manufacturer ID, an 11-bit JEDEC code that identifies the designer of the device. See JEDEC Manufacturer ID. Figure 3.215 shows the ARM value for this field as 0x23B. This value must not be changed.

[0]-Always 1.

Control/Status register, CTRL/STAT

Purpose

Present in all debug port implementations. It provides control to the debug port, and status information about the debug port. JTAG-DP is at address 0x4 when the IR contains DPACC. SW-DP is at address 0b01 on read and write operations when the APnDP bit = 0 and the CTRLSEL bit in the Select Register is set to 0. For information about the CTRLSEL bit, see AP Select register, SELECT.

The Control/Status Register is a RW register, in which some bits have different access rights. Support to some fields in the register is implementation defined.

Attributes

Figure 3.217 shows the bit assignments.

Figure 3.217. Control/Status Register bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 3.239 shows the Control/Status Register bit assignments.

Table 3.239. Control/Status Register bit assignments

BitsAccessFunctionDescription
[31]ROCSYSPWRUPACKSystem powerup acknowledge.
[30]RWCSYSPWRUPREQ

System powerup request.

The reset value is 0.

[29]ROCDBGPWRUPACKDebug powerup acknowledge.
[28]RWCDBGPWRUPREQ

Debug powerup request.

The reset value is 0.

[27]ROCDBGRSTACKDebug reset acknowledge.
[26]RWCDBGRSTREQ

Debug reset request.

The reset value is 0.

[25:24]--Reserved, RAZ/SBZP.
[23:12]RWTRNCNT

Transaction counter.

The reset value is unpredictable.

[11:8]RWMASKLANE

Indicates the bytes to be masked in pushed compare and pushed verify operations.

The reset value is unpredictable.

[7]ROaWDATAERR[a]

This bit is set to 1 if a Write Data Error occurs. It is set if:

  • There is a a parity or framing error on the data phase of a write.

  • A write that the debug port accepted is then discarded without being submitted to the access port.

This bit can only be set to 0 by writing 1 to ABORT.WDERRCLR. XYQ.

The reset value after a powerup reset is 0.

[6]ROaREADOKa

This bit is set to 1 if the response to a previous access port or RDBUFF was OK. It is set to 0 if the response was not OK.

This flag always indicates the response to the last access port read access.

The reset value after a powerup reset is 0.

[5]RO[b]STICKYERR

This bit is set to 1 if an error is returned by an access port transaction. To set this bit to 0:

JTAG-DP

Write 1 to this bit of this register.

SW-DP

Write 1 to ABORT.STKERRCLR.

After a powerup reset this bit is LOW.

[4]ROaSTICKYCMP

This bit is set to 1 when a match occurs on a pushed compare or a pushed verify operation. To set this bit to 0:

JTAG-DP

Write 1 to this bit of this register.

SW-DP

Write 1 to ABORT.STKCMPCLR.

The reset value after a powerup reset is 0.

[3:2]RWTRNMODE

This field sets the transfer mode for access port operations.

After a powerup reset the reset value is unpredictable.

[1]ROaSTICKYORUN

If overrun detection is enabled, this bit is set to 1 when an overrun occurs. To set this bit to 0:

JTAG-DP

Write 1 to this bit of this register.

SW-DP

Write 1 to ABORT.ORUNERRCLR.

After a powerup reset the reset value is 0. See bit[0] of this register.

[0]RWORUNDETECT

This bit is set to 1 to enable overrun detection.

The reset value is 0.

[a] Implemented on SW-DP only. On a JTAG-DP this bit is Reserved, RAZ/SBZP.

[b] RO on SW-DP. On a JTAG-DP, this bit can be read normally, and s 1 to this bit sets the bit to 0.


AP Select register, SELECT

Purpose

Present in all debug port implementations. Its main purpose is to select the current access port and the active 4-word register window in that access port. On a SW-DP, it also selects the debug port address bank.

JTAG-DP

It is at address 0x8 when the IR contains DPACC, and is a RW register.

SW-DP

It is at address 0b10 on write operations when the APnDP bit = 0, and is a WO register. Access to the AP Select Register is not affected by the value of the CTRLSEL bit.

Attributes

Figure 3.218 shows the bit assignments.

Figure 3.218. AP Select Register bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 3.240 shows the bit assignments.

Table 3.240. AP Select Register bit assignments

BitsFunctionDescription
[31:24]APSEL

Selects the current access port.

0x00

Selects the AP connected to master interface 0 of the DAPBUS interconnect.

0x01

Selects the AP connected to master interface 1 of the DAPBUS interconnect, if present.

0x02

Selects the AP connected to master interface 2 of the DAPBUS interconnect, if present.

0x03

Selects the AP connected to master interface 3 of the DAPBUS interconnect, if present.

...

...

...

...

0x1F

Selects the AP connected to master interface 31 of the DAPBUS interconnect, if present.

The reset value is unpredictable.[a]

[23:8]Reserved. SBZ/RAZa.Reserved. SBZ/RAZa.
[7:4]APBANKSEL

Selects the active 4-word register window on the current access port.

The reset value is unpredictable.a

[3:0]DPBANKSEL[b]

Selects the register that appears at DP register 0x4.

0x0

CTRL/STAT, RW.

0x1

DLCR, RW.

0x2

TARGETID, RO.

0x3

DLPIDR, RO.

All other values are reserved. Writing a reserved value to this field is unpredictable.

[a] On a SW-DP the register is write-only, therefore you cannot read the field value.

[b] SW-DP only. On a JTAG-DP this bit is Reserved, SBZ/RAZ.


If APSEL is set to a non-existent access port, all access port transactions return RAZ/WI.

Note

Every ARM Debug Interface implementation must include at least one access port.

Read Buffer register, RDBUFF

Purpose

Present in all debug port implementations. However, there are significant differences in its implementation on JTAG and SW Debug Ports.

JTAG-DP

It is at address 0xC when the IR contains DPACC, and is a RAZ, RAZ/WI register.

SW-DP

It is at address 0b11 on read operations when the APnDP bit = 0 and is a RO register. Access to the Read Buffer is not affected by the value of the CTRLSEL bit in the SELECT Register.

Attributes
Read Buffer implementation and use on a JTAG-DP

On a JTAG-DP, the read buffer is RAZ/WI.

The read buffer is architecturally defined to provide a debug port read operation that does not have any side effects. This means that a debugger can insert a debug port read of the read buffer at the end of a sequence of operations, to return the final read result and ACK values.

Read Buffer implementation and use on a SW-DP

On a SW-DP, performing a read of the read buffer captures data from the access port, presented as the result of a previous read, without initiating a new access port transaction. This means that reading the read buffer returns the result of the last access port read access, without generating a new AP access.

After you read the read buffer, its contents are no longer valid. The result of a second read of the read buffer is unpredictable.

If you require the value from an access port register read, that read must be followed by one of:

  • A second access port register read. You can read the CSW if you want to ensure that this second read has no side effects.

  • A read of the DP Read Buffer.

This second access, to the access port or the debug port depending on which option you use, stalls until the result of the original access port read is available.

Data Link Control Register, DLCR (SW-DP only)

Purpose

Present in any SW-DP implementation. Selects the operating mode of the physical serial port connection to the SW-DP.

It is a read/write register at address 0b01 on read and write operations when the CTRLSEL bit in the Select Register is set to 1. For information about the CTRLSEL bit see AP Select register, SELECT.

Note

When the CTRLSEL bit is set to 1, to enable access to the WCR, the DP Control/Status Register is not accessible.

Many features of the Data Link Control Register are implementation defined.

Attributes

Figure 3.219 shows the bit assignments.

Figure 3.219. Data Link Control Register bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 3.241 shows the bit assignments.

Table 3.241. Data Link Control Register bit assignments

BitsFunctionDescription
[31:10]-Reserved, SBZ/RAZ.
[9:8]TURNROUND

Turnaround tristate period, see Turnaround tristate period, TURNROUND, bits [9:8].

The reset value is 0b00.

[7:6]WIREMODE

Identifies the operating mode for the wire connection to the debug port, see Wire operating mode, WIREMODE, bits [7:6].

The reset value is 0b01.

[5:3]-Reserved, SBZ/RAZ.
[2:0]PRESCALERReserved, SBZ/RAZ.

Turnaround tristate period, TURNROUND, bits [9:8]

This field defines the turnaround tristate period. This turnaround period permits pad delays when using a high sample clock frequency. Table 3.242 shows the permitted values of this field, and their meanings.

Table 3.242. Turnaround tristate period field bit definitions

TURNROUND[a]Turnaround tristate period
0b001 sample period
0b012 sample periods
0b103 sample periods
0b114 sample periods

[a] Bits[9:8] of the DLCR.


Wire operating mode, WIREMODE, bits [7:6]

This field identifies SW-DP as operating in Synchronous mode only. This field is required, and Table 3.243 shows the permitted values of the field, and their meanings.

Table 3.243. Wire operating mode bit definitions

WIREMODE[a]Wire operating mode
0b00Reserved.
0b01Synchronous, that is, no oversampling.
0b1XReserved.

[a] Bits[7:6] of the DLCR.


Target Identification register, TARGETID (SW-DP only)

Purpose

Provides information about the target when the host is connected to a single device. It is:

  • A RO register.

  • Accessed by a read of DP register 0x4 when the DPBANKSEL bit in the SELECT Register is set to 0x2.

The value of this register reflects the value of the targetid[31:0] input.

Attributes

Figure 3.220 shows the bit assignments.

Figure 3.220. Target Identification register bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 3.244 shows the bit assignments.

Table 3.244. Target Identification register bit assignments

BitsFunctionDescription
[31:28]TREVISIONTarget revision.
[27:12]TPARTNO

Configuration-dependent

This value is assigned by the designer of the part and must be unique to that part.

[11:1]TDESIGNERImplementation defined. This field identifies the designer of the part. The value is based on the code assigned to the designer by JEDEC standard JEP-106, as used in IEEE 1149.1.
[0]-Reserved, RAO.

Data Link Protocol Identification Register, DLPIDR (SW-DP only)

Purpose

Provides information about the Serial Wire protocol version. It is:

  • A RO register.

  • Accessed by a read of DP register 0x4 when the DPBANKSEL bit in the SELECT Register is set to 0x3.

The contents of this register are data link defined.

Attributes

Figure 3.221 shows the bit assignments.

Figure 3.221. Data Link Protocol Identification Register bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 3.245 shows the bit assignments.

Table 3.245. Data Link Protocol Identification Register bit assignments

BitsFunctionDescription
[31:28]Target Instance

Configuration-dependent

This field defines a unique instance number for this device within the system. This value must be unique for all devices that are connected together in a multi-drop system with identical values in the TREVISION fields in the TARGETID Register. The value of this field reflects the value of the instanceid[3:0] input.

[27:4]-Reserved.
[3:0]Protocol Version

Defines the serial wire protocol version. This value is 0x1, which indicates SW protocol version 2.


Read Resend register, RESEND (SW-DP only)

Purpose

Present in any SW-DP implementation. It enables read data recovery from a corrupted debugger transfer, without repeating the original AP transfer.

It is a 32-bit read-only register at address 0b10 on read operations. Access to the Read Resend Register is not affected by the value of the DPBANKSEL bit in the SELECT Register.

Performing a read to the RESEND register does not capture new data from the access port. It returns the value that was returned by the last AP read or DP RDBUFF read.

Reading the RESEND register enables read data recovery from a corrupted transfer without having to re-issue the original read request or generate a new DAP or system level access.

The RESEND register can be accessed multiple times. It always returns the same value until a new access is made to the DP RDBUFF register or to an access port register.

Attributes

JTAP-DP register descriptions

For more information about JTAG-DP registers, their features, and how to access them, see the ARM® Debug Interface Architecture Specification, ADIv5.0 to ADIv5.2. Also see Common debug port features and registers.

Copyright © 2011-2013 ARM. All rights reserved.ARM DDI 0480F
Non-ConfidentialID100313