ARM CoreSight SoC-400 Technical Reference ManualRevision: r3p1
Home > Programmers Model > CTI register descriptions > CTI Trigger 1 to Channel Enable register

3.15.7. CTI Trigger 1 to Channel Enable register

The CTIINEN1 register characteristics are:

Purpose

Enables the signaling of an event on CTM channels when the core issues a trigger, ctitrigin, to the CTI. There is a bit for each of the four channels implemented. This register does not affect the application trigger operations.

Usage constraints

There are no usage constraints.

Configurations

This register is available in all configurations.

Attributes

See the register summary in Table 3.151.

Figure 3.149 shows the bit assignments.

Figure 3.149. CTIINEN1 register bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 3.158 shows the bit assignments.

Table 3.158. CTIINEN1 register bit assignments

BitsNameFunction
[31:4]Reserved

-

[3:0]TRIGINEN

Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels. On writes, for each bit:

0

Input trigger 1 events are ignored by the corresponding channel.

1

When an event is received on input trigger 1, ctitrigin[1], generate an event on the channel corresponding to this bit.


Copyright © 2011-2013 ARM. All rights reserved.ARM DDI 0480F
Non-ConfidentialID100313
PDF file icon  PDF version
Home > Programmers Model > CTI register descriptions > CTI Trigger 1 to Channel Enable register