4.2.4. Operation in JTAG-DP mode

When operating as a JTAG-DP this follows the JTAG-DP as defined in the ARM® Debug Interface Architecture Specification, ADIv5.0 to ADIv5.2. It also contains an explanation of its programmers model, capabilities, and features.

The JTAG-DP contains a debug port state machine that controls the JTAG-DP mode operation, including controlling the scan chain interface that provides the external physical interface to the JTAG-DP. It is based closely on the JTAG TAP State Machine. See IEEE Std 1149.1-2001.

Overview

The JTAG-DP IEEE 1149.1 compliant scan chains are used to read or write register information. A pair of scan chain registers accesses the main control and access registers within the Debug Port. They are:

  • DPACC, for DP accesses.

  • APACC, for AP accesses. An APACC access might access a register of a debug component of the system to which the interface is connected.

The scan chain model implemented by a JTAG-DP has the concepts of capturing the current value of APACC or DPACC, and of updating APACC or DPACC with a new value. An update might cause a read or write access to a DAP register that might then cause a read or write access to a debug register of a connected debug component. For information on the operations available on JTAG-DP, see the ARM® Debug Interface Architecture Specification, ADIv5.0 to ADIv5.2. For the registers of the JTAG-DP, see JTAP-DP register descriptions.

Implementation-specific information

The implementation-specific information is described in Operation in JTAG-DP mode.

Physical interface

Table 4.1 shows the physical interface for JTAG-DP and the relationship to the signal references in the ARM® Debug Interface Architecture Specification, ADIv5.0 to ADIv5.2. The JTAG-DP interface defined in the ARM® Debug Interface Architecture Specification, ADIv5.0 to ADIv5.2 permits an optional return clock signal. However, the CoreSight SoC-400 JTAG-DP implementation does not include a return clock signal.

Table 4.1. JTAG-DP physical interface

Implementation signal name, JTAG-DPADIv5.2 signal name, JTAG-DPTypeJTAG-DP signal description
tdiDBGTDIInputDebug data in
tdoDBGTDOOutputDebug data out
swclktckTCKInputDebug clock
swditmsDBGTMSInputDebug mode select
ntrstDBGTRSTnInputDebug TAP reset

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