A.2.3. APB synchronous bridge signals

Table A.13 shows the APB synchronous bridge signals.

Table A.13. APB synchronous bridge signals

Signal

Type

Clock domain

Description

pclk

Input

pclkAPB clock signal for all downstream APB debug interfaces.

presetn

Input

pclkAPB reset.
pclkensInputpclkAPB clock enable.
pselsInputpclkAPB select. Indicates that the slave interface is selected and a data transfer is required.
penablesInputpclkAPB enable. Indicates the second and subsequent cycles of an APB transfer initiated on slave interface.
pwritesInputpclkAPB RW transfer. Indicates an APB write access when HIGH and an APB read access when LOW.
paddrs[31:0]InputpclkAPB address bus.
pwdatas[31:0]InputpclkAPB write data.
pclkenmInputpclkAPB clock enable.
preadymInputpclkAPB ready. The slave device uses this signal to extend an APB transfer.
pslverrmInputpclkAPB transfer error. Indicates a transfer failure. The APB peripherals are not required to support the pslverr pin.
prdatam[31:0]InputpclkAPB read data. The selected slave drives this bus during read cycles.
csysreq[a]InputpclkClock powerdown request.
preadysOutputpclkAPB ready. The slave interface uses this signal to extend an APB transfer.
pslverrsOutputpclkAPB transfer error. Indicates a transfer failure. The APB peripherals are not required to support the pslverr pin.
prdatas[31:0]OutputpclkAPB read data. The slave interface drives this bus during read cycles.
pselmOutputpclkAPB select. Indicates that the slave device connected to master interface is selected and a data transfer is required.
penablemOutputpclkAPB enable. Indicates the second and subsequent cycles of an APB transfer initiated by master interface.
pwritemOutputpclkAPB RW transfer. Indicates an APB write access when HIGH and an APB read access when LOW.
paddrm[31:0]OutputpclkAPB address bus.
pwdatam[31:0]OutputpclkAPB write data. The APB master interface drives this bus.
csysack[a]OutputpclkClock powerdown acknowledge.
cactive[a]OutputpclkClock is required when driven HIGH.

[a] This signal is only present if you configure this component to have an LPI.


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