A.5.3. Event asynchronous bridge signals

Table A.31 shows the event asynchronous bridge signals.

Note

Master clock is the domain that drives the slave interface to this bridge.

Table A.31. Event asynchronous bridge signals

NameTypeClock domainDescription
clksInputclksClock.
clkensInputclksClock enable.
resetsnInputclksReset.
clkmInputclkmClock.
clkenmInputclkmClock enable.
resetmnInputclkmReset.
eventsInputclksEvent request.
eventackmInputclkmEvent acknowledge.
eventacksOutputclksEvent acknowledge.
eventmOutputclkmEvent request.

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