A.2.2. APB asynchronous bridge signals

Table A.11 shows the APB asynchronous bridge signals.

Table A.11. APB asynchronous bridge signals

Signal

Type

Clock domain

Description

pclks

Input

pclksAPB clock.

presetsn

Input

pclksAPB reset.
pclkensInputpclksAPB clock enable.
pclkmInputpclkmAPB clock.
presetmnInputpclkmAPB reset.
pclkenmInputpclkmAPB clock enable.
pselsInputpclksAPB select. Indicates that the slave interface is selected and a data transfer is required.
penablesInputpclksAPB enable. Indicates the second and subsequent cycles of an APB transfer initiated on slave interface.
pwritesInputpclksAPB RW transfer. Indicates an APB write access when HIGH and an APB read access when LOW.
paddrs[31:0]InputpclksAPB address bus.
pwdatas[31:0]InputpclksAPB write data.
preadymInputpclkmAPB ready. The slave device uses this signal to extend an APB transfer.
pslverrmInputpclkmAPB transfer error. Indicates a transfer failure. The APB peripherals are not required to support the pslverr pin.
prdatam[31:0]InputpclkmAPB read data. The selected slave drives this bus during read cycles.
csysreq[a]InputpclkmClock powerdown request.
preadysOutputpclksAPB ready. The slave interface uses this signal to extend an APB transfer.
pslverrsOutputpclksAPB transfer error. Indicates a transfer failure. The APB peripherals are not required to support the pslverr pin.
prdatas[31:0]OutputpclksAPB read data. The slave interface drives this bus during read cycles.
pselmOutputpclkmAPB select. Indicates that the slave device connected to the master interface is selected and a data transfer is required.
penablemOutputpclkmAPB enable. Indicates the second and subsequent cycles of an APB transfer that the master interface initiates.
pwritemOutputpclkmAPB RW transfer. Indicates an APB write access when HIGH and an APB read access when LOW.
paddrm[31:0]OutputpclkmAPB address bus.
pwdatam[31:0]OutputpclkmAPB write data. The APB master interface drives this bus.
csysack[a]OutputpclkmClock powerdown acknowledge.
cactive[a]OutputpclkmClock is required when driven HIGH.

[a] This signal is present only if you configure this component to have a low-power interface, and it configured for master-only or full.


Cross-domain connections

The APB asynchronous bridge can be configured as a separate master interface component and slave interface component. If you configure the bridge in this way, then you must connect the two components as Table A.12 shows.

Table A.12 shows APB asynchronous bridge cross-domain connections.

Table A.12. APB asynchronous bridge cross-domain connections

Slave component signal TypeMaster component signalType
apbm_req_async Outputapbs_req_asyncInput
apbm_ack_async Inputapbs_ack_asyncOutput
apbm_fwd_data_async Outputapbs_fwd_data_async Input
apbm_rev_data_async Inputapbs_rev_data_async Output

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