3.17.4. APB-AP registers description

This section describes the following APB-AP registers:

APB-AP Control/Status Word register, CSW, 0x00

Purpose

Configures and controls transfers through the APB interface.

Attributes

Figure 3.210 shows the bit assignments.

Figure 3.210. APB-AP Control/Status Word register bit assignments

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Table 3.229 shows the bit assignments.

Table 3.229. APB Control/Status Word register bit assignments

BitsTypeNameFunction
[31]RWDbgSwEnable

Software access enable.

Drives pdbgswen to enable or disable software access to the Debug APB bus in the APB interconnect.

0

Disable software access.

1

Enable software access.

The reset value is 0. On exit from reset, the default value is 1 to enable software access.

[30:12]--Reserved, SBZ.
[11:8]RWMode

Specifies the mode of operation.

0b0000

Normal download or upload model.

0b0001-0b1111

Reserved, SBZ.

The reset value is 0b0000.

[7]ROTrInProgTransfer in progress. This field indicates whether a transfer is currently in progress on the APB master port.
[6]RODeviceEn

Indicates the status of the deviceen input.

  • If APB-AP is connected to the Debug APB, a bus connected only to debug and trace components, it must be permanently enabled by tying deviceen HIGH. This ensures that trace components can still be programmed when dbgen is LOW. In practice, the APB-AP is normally used in this way.

  • If APB-AP is connected to a system APB dedicated to the non-secure world, deviceen must be connected to dbgen.

  • If APB-AP is connected to a system APB dedicated to the secure world, deviceen must be connected to spiden.

[5:4]RWAddrInc

Auto address increment and packing mode on Read or Write data access. Increment occurs in word steps. Does not increment if the transaction completes with an error response or the transaction is aborted.

Auto address incrementing is not performed on accesses to banked data registers 0x10-0x1C.

The status of these bits is ignored in this case.

0b11

Reserved.

0b10

Reserved.

0b01

Increment.

0b00

Auto increment OFF.

The reset value is 0b00.

[3]--Reserved, SBZ.
[2:0]ROSize

Size of the access to perform.

Fixed at 0b010, 32 bits.

The reset value is 0b010.


APB-AP Transfer Address Register, TAR, 0x04

Purpose

Holds the address of the current transfer.

Attributes

Figure 3.211 shows the bit assignments.

Figure 3.211. APB-AP Transfer Address register bit assignments

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Writes to the TAR from the DAP interface, write to bits [31:2] only. Bits [1:0] of dapwdata are ignored on writes to the TAR.

Table 3.230 shows the bit assignments.

Table 3.230. APB-AP Transfer Address register bit assignments

BitsTypeNameFunction
[31:2]RWAddress[31:2]

Address[31:2] of the current transfer.

paddr[31:2]=TAR[31:2] for accesses from Data RW Register at 0x0C.

paddr[31:2]=TAR[31:4]+dapcaddr[3:2] for accesses from Banked Data Registers at 0x10-0x1C and 0x0C.

[1:0]-Reserved, SBZSet to 0b00. SBZ/RAZ.

APB-AP Data Read/Write register, DRW, 0x0C

Table 3.231 shows the bit assignments.

Table 3.231. ABP-AP Data Read/Write register bit assignments

BitsTypeNameFunction
[31:0]RWData

The possible modes are:

Write mode

Data value to write for the current transfer.

Read mode

Data value read from the current transfer.


APB-AP Banked Data registers, BD0-BD3, 0x10-0x1C

Purpose

BD0-BD3 provide a mechanism for directly mapping through DAP accesses to APB transfers without having to rewrite the TAR within a four-word boundary. For example, BD0 RW from TAR, and BD1 from TAR+4.

Attributes

Table 3.232 shows the bit assignments.

Table 3.232. APB-AP Banked Data registers bit assignments

BitsTypeNameFunction
[31:0]RWData

If dapcaddr[7:4] = 0x0001, it is accessing APB-AP registers in the range 0x10-0x1C, and the derived paddr[31:0] is:

Write mode

Data value to write for the current transfer to external address TAR[31:4] + dapcaddr[3:2] + 0b00.

Read mode

Data value read from the current transfer from external address TAR[31:4] + dapcaddr[3:2] + 0b00.

Auto address incrementing is not performed on DAP accesses to BD0-BD3.

The reset value is 0x00000000.


APB-AP Debug Base Address register, BASE, 0xF8

Table 3.223 shows the bit assignments.

Table 3.233. Debug Base Address register bit assignments

BitsTypeNameFunction
[31:0]RODebug APB ROM Address

Base address of a ROM table. The ROM provides a look-up table for system components.

Bit[1] is SBO. Set bit[0] to 1 if there are debug components on this bus. For most debug APB systems, this value is 0x80000003.


APB-AP Identification Register

Figure 3.212 shows the bit assignments.

Figure 3.212. APB-AP Identification register bit assignments

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Table 3.234 shows the bit assignments.

Table 3.234. APB-AP Identification register bit assignments

BitsTypeName
[31:28]RO

Revision.

0x4. This component is at r0p5.

[27:24]ROJEDEC bank. 0x4 indicates ARM.
[23:17]ROJEDEC code. 0x3B indicates ARM.
[16]ROMemory AP. 0x1 indicates a standard register map is used.
[15:8]-Reserved, SBZ.
[7:0]RO

Identity value.

The reset value is 0x03 for APB-AP.


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