3.17.1. JTAG-AP register descriptions

All the registers are described in ARM® Debug Interface Architecture Specification, ADIv5.0 to ADIv5.2.

JTAG-AP Control/Status Word register, CSW, 0x00

Purpose

Configures and controls transfers through the JTAG interface.

Attributes

Figure 3.195 shows the bit assignments.

Figure 3.195. JTAG-AP CSW register bit assignments

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Table 3.210 shows the bit assignments. The register must not be modified while there are outstanding commands in the Write FIFO.

Table 3.210. JTAG-AP CSW register bit assignments

BitsTypeNameFunction
[31]ROSERACTV

JTAG serializer active.

The reset value is 0b0.

[30:28]ROWFIFOCNT

Outstanding write FIFO byte count.

The reset value is 0b000.

[27]--Reserved, SBZ.
[26:24]RORFIFOCNT

Outstanding read FIFO byte count.

The reset value is 0b000.

[23:4]--Reserved, SBZ.
[3]ROPORTCONNECTED

PORT connected. AND of portconnected inputs of currently selected ports.

The reset value is 0.

[2]ROSRSTCONNECTED[a]

SRST connected.

AND of srstconnected inputs of currently selected ports. If multiple ports are selected, it is the AND of all the srstconnected inputs from the selected ports.

The reset value is 0.

[1]RWTRST_OUT

TRST assert, not self clearing. The JTAG TAP controller reset.

The reset value is 0.

[0]RWSRST_OUT

SRST assert, not self clearing. Core reset.

The reset value is 0.

[a] SRSTCONNECTED is a strap pin on the multiplexer inputs. It is set to 1 to indicate that the target JTAG device supports individual SRST controls.


JTAG-AP Port Select register, PORTSEL, 0x04

Purpose

Enables ports if connected and the slave port is currently enabled. The Port Select register must be written when the following conditions are met:

  • The TCK engine is idle.

  • SERACTV is 0.

  • WFIFO and WFIFOCNT are 0, that is, they are empty.

Writing at other times can generate unpredictable results.

Attributes

Figure 3.196 shows the bit assignments.

Figure 3.196. JTAG-AP Port Select register bit assignments

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Table 3.211 shows the bit assignments.

Table 3.211. JTAG-AP Port Select register bit assignments

BitsTypeNameFunction
[31:8]--Reserved SBZ.
[7:0]RWPORTSEL

Port Select.

The reset value is 0x00.


JTAG-AP Port Status register, PSTA, 0x08

Purpose

A sticky register that captures the state of a connected and selected port on every clock cycle. If a connected and selected port is disabled or powered down, even transiently, the corresponding bit in the Port Status register is set. It remains 1 until the corresponding bit is set o 1.

Attributes

Figure 3.197 shows the bit assignments.

Figure 3.197. JTAG-AP Port Status register bit assignments

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Table 3.212 shows the bit assignments.

Table 3.212. JTAG-AP Port Status register bit assignments

BitsTypeNameFunction
[31:8]--Reserved, SBZ.
[7:0]RWPSTA

Port Status.

The reset value is 0x00.


JTAG-AP Byte FIFO registers, BFIFOn, 0x10-0x1C

Purpose

Word interface to one, two, three, or four parallel byte entries in the byte command FIFO, LSB first. The DAP internal bus is a 32-bit interface with no SIZE field. An address decoding designates size, because the JTAG-AP engine JTAG protocol is byte encoded. Writes to the BFIFOx that are larger than the current write FIFO depth stall on dapready in normal mode. Reads to the BFIFOx that are larger than the current read FIFO depth stall on dapready in normal mode. For reads less than the full 32 bits, the upper bits are 0. For example, for a 24-bit read, daprdata[31:24] is 0x00.

Attributes

JTAG-AP Identification Register, IDR

Figure 3.198 shows the bit assignments.

Figure 3.198. JTAG-AP Identification Register bit assignments

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Table 3.213 shows the bit assignments.

Table 3.213. JTAG-AP Identification Register bit assignments

BitsTypeNameValueFunction
[31:28]RORevision0x2r0p3
[27:24]ROJEDEC bank0x4Designed by ARM
[23:17]ROJEDEC code0x3BDesigned by ARM
[16]ROMem AP0x0Is a Mem AP
[15:8]-Reserved0x00-
[7:0]ROIdentity value0x10JTAG-AP

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