A.5.2. Cross Trigger Matrix signals

Table A.30 shows the CTM signals.

Table A.30. CTM signals

NameTypeClock domainDescription
cihsbypass0[3:0]InputctmclkHandshaking bypass port 0.
cihsbypass1[3:0]InputctmclkHandshaking bypass port 1.
cihsbypass2[3:0]InputctmclkHandshaking bypass port 2.
cihsbypass3[3:0]InputctmclkHandshaking bypass port 3.
cisbypass0InputctmclkSync bypass for port 0.
cisbypass1InputctmclkSync bypass for port 1.
cisbypass2InputctmclkSync bypass for port 2.
cisbypass3InputctmclkSync bypass for port 3.
ctmchin0[3:0]InputctmclkChannel in port 0.
ctmchin1[3:0]InputctmclkChannel in port 1.
ctmchin2[3:0]InputctmclkChannel in port 2.
ctmchin3[3:0]InputctmclkChannel in port 3.
ctmchoutack0[3:0]InputctmclkChannel out acknowledge port 0.
ctmchoutack1[3:0]InputctmclkChannel out Acknowledge port 1.
ctmchoutack2[3:0]InputctmclkChannel out acknowledge port 2.
ctmchoutack3[3:0] InputctmclkChannel out acknowledge port 3.
ctmclkInputctmclkClock.
ctmclkenInputctmclkClock enable.
ctmresetn InputctmclkReset.
seInputN/AScan enable.
ctmchinack0[3:0] OutputctmclkChannel in acknowledge port 0.
ctmchinack1[3:0] OutputctmclkChannel in acknowledge port 1.
ctmchinack2[3:0] OutputctmclkChannel in acknowledge port 2.
ctmchinack3[3:0] OutputctmclkChannel in acknowledge port 3.
ctmchout0[3:0]OutputctmclkChannel out port 0.
ctmchout1[3:0]OutputctmclkChannel out port 1.
ctmchout2[3:0]OutputctmclkChannel out port 2.
ctmchout3[3:0]OutputctmclkChannel out port 3.

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