3.11.2. ETB Status register

The STS register characteristics are:

Purpose

Indicates the status of the ETB.

Usage constraints

There are no usage constraints.

Configurations

This register is available in all configurations.

Attributes

See the register summary in Table 3.79.

Figure 3.74 shows the bit assignments.

Figure 3.74. STS register bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 3.81 shows the bit assignments.

Table 3.81. STS register bit assignments

BitsNameFunction
[31:4]Reserved

-

[3]FtEmpty

Formatter pipeline is empty. All data is stored to RAM.

0

Formatter pipeline is not empty.

1

Formatter pipeline is empty.

[2]AcqComp

The acquisition complete flag indicates that the capture is completed when the formatter stops because of any of the methods defined in the FFCR, or CTL.TraceCaptEn is 0. This sets FFSR.FtStopped to 1.

0

Acquisition is not complete.

1

Acquisition is complete.

[1]Triggered

The Triggered bit is set when the component observes a trigger during programming the FFCR.

Note

This field does not indicate that the formatter embedded a trigger in the trace data.

0

A trigger is not observed.

1

A trigger is observed.

[0]Full

The flag indicates whether the RAM is full or not.

0

The RAM write pointer is not wrapped around. The RAM is not full.

1

The RAM write pointer is wrapped around. The RAM is full.


Copyright © 2011-2013 ARM. All rights reserved.ARM DDI 0480F
Non-ConfidentialID100313