4.5.1. Clock and reset

The two synchronous clock domains must use the same clock input. Clock enable inputs are used to indicate the relative speeds of the two clock domains. The clocks and resets of the DAPBUS synchronous bridge are:

dapclk

Clock.

dapresetn

Active-LOW reset. This is asynchronously asserted and must be synchronously deasserted.

dapclkens

Clock enable for the slave interface.

dapclkenm

Clock enable for the master interface.

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