4.7.1. Clock and reset

The AXI-AP operates in a single clock domain, which must be used for both the DAPBUS interface and the AXI interface. The clock and reset signals of the AHB-AP are:

clk

Clock

resetn

Active-LOW reset. This is asynchronously asserted and must be synchronously deasserted.

On AXI-AP reset, the entire AXI-AP module is reset and the transaction history is lost. ARM recommends that reset is not asserted while an AXI transfer is in progress. However, AXI-AP permits reset to be asserted with the understanding that all transaction history is lost.

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