4.7.5. Error responses

This section describes the following:

AXI initiated error responses

An error response received on the AXI master interface propagates onto the DAP bus as the transfer is completed.

For 64-bit data transfer, a sequence of two reads or writes must be generated on the DAP bus for a single 64-bit access on the AXI interface. For reads, the first read request on the DAP bus sends a read request on the AXI interface while for writes, a write access is sent on the AXI interface only after two write requests are received on the DAP bus.

Therefore, an error response received for a read request is for the first read request on the DAP bus while an error response received for a write request is for the second write request on the DAP bus.

AP initiated error response

AXI-AP writes after an abort

After a DP-initiated abort operation is carried out, and an external transfer is still pending, that is, the transfer in progress bit remains HIGH, all writes to the AXI-AP return an error response which you can ignore.

AXI-AP writes return an error until the transfer in progress, the TrInProg bit, is set to 0 when the system transfer completes.

AXI-AP reads after a 64-bit AXI read sequence is broken

Read requests from the DAP bus must access both BDx registers of the pair, and must access the lower-numbered register first. For a DRW, two write requests are required to get the entire 64-bit word from AXI interface.

All other accesses, such as a read followed by a write access to the same or different registers, return an error response to the DP.

AXI-AP writes after a 64-bit write sequence is broken

Write requests from the DAP interface must access both BDx registers of the pair and must access the lower-numbered register first. For a DRW, two write requests are required to build a 64-bit packet as write data on the AXI interface.

All other accesses, such as a write followed by another R/W access to different registers, return an error response.

For example, after accessing DRW, the next access on the DAP bus must be a write to DRW. Any other access returns an error response.

Similarly, after accessing BD0, the next access must be a write to BD1. Any other access returns an error response.

Aborted AXI barrier transaction

It is possible to abort a barrier transaction that has not yet completed. When the abort request is generated, the DAPBUS transaction is completed in the next cycle. However the CSW.TrInPrg bit remains set to indicate that the AXI interface is busy waiting to complete the transaction. While the AXI interface is busy, a R/W request to DRW or BDx registers that results in a transaction on the AXI interface, causes the AXI-AP to return an error response to the DP.

AXI and AP initiated error responses

If an error response is given on the DAPBUS slave interface and TrInProg is LOW in the CSW Register, the error is from either:

  • A system error response if dbgen and spiden permit the transfer to be initiated.

  • An AXI-AP error response if dbgen and spiden do not permit the transfer.

Table 4.6 shows the difference between an AXI and an AP initiated error response.

Table 4.6. Difference between AXI and AP initiated error response

CSW.Prot[1]spidendbgenError response fromReason
XX0AXI-APAll transfers blocked
001AXI-APSecure transfers blocked
011SystemSecure transfer produced an error response
1X1SystemNon secure transfer produced an error response

If an error response is given and TrInProg is HIGH, then the error is from an access port error response. This case can only occur after the initiation of an abort when the system transfer has not completed.

AXI transfers

The AMBA4 AXI compliant Master Port supports the following features:

  • Bursts of single transfer.

  • Master processes one transaction at a time in the order they are issued.

  • No out-of-order transactions.

  • No issuing of multiple outstanding addresses.

Burst length

The AXI-AP supports burst length of one transfer only. ARLEN[3:0] and AWLEN[3:0] are always 0b0000.

Packed 8 or 16-bit transfers are treated as individual burst lengths of one transfer at the AXI interface. This ensures that there are no issues with boundary wrapping to avoid additional AXI-AP complexity.

Burst size

Supported burst sizes are:

  • 8-bit.

  • 16-bit.

  • 32-bit.

  • 64-bit.

Burst type

ARBURST and AWBURST signals are always 0b00.

Because only bursts of one transfer are supported, burst type has no meaning in this context.

Atomic accesses

AXI-AP supports normal accesses only.

ARLOCK and AWLOCK signals are always 0b00.

Unaligned accesses

Unaligned accesses are not supported. Depending on the size of the transfers, addresses must be aligned.

  • For 16-bit half word transfers:

    • Base address 0x01 is aligned and AxADDR[7:0] = 0x00.

    • Base address 0x02 is retained and AxADDR[7:0] = 0x02.

  • For 32-bit word transfers:

    • Base address 0x01 to 0x03 is aligned and AxADDR[7:0] = 0x00.

    • Base address 0x04 is retained and AxADDR[7:0] = 0x04.

  • For 64-bit word transfers:

    • Base address 0x04 is aligned and AxADDR[7:0] = 0x00.

    • Base address 0x08 is retained and AxADDR[7:0] = 0x08.

For example, for 16-bit transfers, addresses must be aligned to a 16-bit half-word boundary, for 32-bit word transfers, addresses must be word-aligned, and for 64-bit double word transfers, addresses must be double-word aligned.

Packed transfers

The DAPBUS interface is a 32-bit data bus. However, 8-bit or 16-bit transfers can be formed on AXI according to the size field in the CSW register, 0x000. The AddrInc field in the CSW Register permits optimized use of DAPBUS to reduce the number of accesses to the DAP. It indicates whether the entire data word can be used to pack more than one transfer. If packed transfers are initiated, then address incrementing is automatically enabled. Multiple transfers are carried out in sequential addresses, with the size of the address increment based on the size of the transfer.

Examples of the transactions are:

For an unpacked 16-bit write at a base address of base 0x2, that is, CSW[2:0]=0b001, CSW[5:4]=0b01, WDATA[31:16] is written from bits [31:16] in the DRW register.

For an unpacked 8-bit read at a base address of base 0x1, that is, CSW[2:0]=0b000, CSW[5:4]=0b01, RDATA[31:16] and RDATA[7:0] are zero, RDATA[15:8] contains read data.

For a packed byte write at base address of base 0x2, that is, CSW[2:0]=0b000 and CSW[5:4]=0b10, four write transfers are initiated, and the order of data that is sent is:

  • WDATA[23:16], from DRW[23:16] to AWADDR[31:0]=0x00000002.

  • WDATA[31:24], from DRW[31:24] to AWADDR[31:0]=0x00000003.

  • WDATA[7:0], from DRW[7:0] to AWADDR[31:0]=0x00000004.

  • WDATA[15:8], from DRW[15:8] to AWADDR[31:0]=0x00000005.

For a packed half-word read at a base address of base 0x2, that is, CSW[2:0]=0b001, CSW[5:4]=0b10, two read transfers are initiated:

  • RDATA[31:16] is stored into DRW[31:16] from ARADDR[31:0]=0x00000002.

  • RDATA[15:0] is stored into DRW[15:0] from ARADDR[31:0]=0x00000004.

The AXI-AP only asserts DAPREADY HIGH when all packed transfers from the AXI interface have completed.

If the current transfer is aborted or the current transfer receives an ERROR response, the AXI-AP does not complete the subsequent packed transfers and returns DAPREADY HIGH immediately after the current packed transfer.

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