5.3.1. Clock and reset

The APB synchronous bridge operates in a single clock domain with one asynchronous reset. The clocks and resets of the APB synchronous bridge are:

pclk

Clock.

presetn

Active-LOW reset. This is asynchronously asserted and must be synchronously deasserted.

pclkenm

Clock enable for master interface.

pclkens

Clock enable for slave interface.

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