10.3.2. Memory BIST interface

Table 10.2 shows the Memory BIST interface ports.

Table 10.2. ETB Memory BIST interface ports

NameTypeDescription
mbistaddr [CSETB_ADDR_WIDTH-1:0]Input

Address bus for the external BIST controller, active when mteston is HIGH.

CSETB_ADDR_WIDTH defines the address bus width used, and therefore the RAM depth supported.

mbistceInputActive-HIGH chip select for external BIST controller, active when mteston is HIGH.
mbistdin[31:0]InputWrite data bus for external BIST controller, active when mteston is HIGH.
mbistdout[31:0]OutputRead data bus for external BIST controller, active when mteston is HIGH.
mbistweInputActive-HIGH write enable for external BIST controller, active when mteston is HIGH.
mtestonInputEnable signal for the external BIST controller.

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