8.2.1. Clocks and resets

The clock and reset signals of the CTI are:

cticlk

CTI clock.

ctiresetn

Active-LOW reset. This is asynchronously asserted and must be synchronously deasserted.

cticlken

CTI clock enable.

pclkdbg

APB interface clock.

pclkendbg

APB clock enable.

presetdbgn

APB interface active-LOW reset. This is asynchronously asserted and must be synchronously deasserted.

The CTI includes an asynchronous bridge between the cticlk and pclkdbg domains, which can be disabled. It also includes configurable synchronizers to enable trigger inputs, trigger outputs, and the channel interface to connect to components in different clock domains. For more information on configuring these features, see the ARM® CoreSight™ SoC-400 Integration Manual.

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