A.6.2. Embedded Trace Buffer signals

Table A.33 shows the ETB signals.

Table A.33. ETB signals

NameTypeClock domainDescription
afreadysInputatclkATB data flush complete.
atbytess[1:0]InputatclkATB number of valid bytes, LSB aligned, on the slave port.
atclkInputatclkATB clock.
atclkenInputatclkATB clock enable.
atdatas[31:0]InputatclkATB trace data.
atids[6:0]InputatclkATB ID for the current trace data.
atresetnInputatclkATB reset for the atclk domain.
atvalidsInputatclkATB valid signals present.
flushinInputatclkFlush input from the CTI.
mbistaddr[AW-1:0]InputatclkMemory BIST address.
mbistceInputatclkMemory BIST chip enable.
mbistdin[31:0]InputatclkMemory BIST data in.
mbistweInputatclkMemory BIST write enable.
mtestonInputatclkMemory BIST test is enabled.
paddrdbg[11:2]InputpclkdbgDebug APB address bus.
paddrdbg31 InputpclkdbgEnables components to distinguish between internal accesses from system software and external accesses from a debugger.
pclkdbgInputpclkdbgDebug APB clock.
pclkendbgInputpclkdbgDebug APB clock enable.
penabledbgInputpclkdbgDebug APB enable signal. Indicates second and subsequent cycles.
presetdbgnInputpclkdbgDebug APB reset.
pseldbgInputpclkdbgDebug APB component select.
pwdatadbg[31:0]InputpclkdbgDebug APB write data bus.
pwritedbgInputpclkdbgDebug APB write transfer.
seInputN/AScan enable.
triginInputatclkTrigger input from the CTI.
acqcompOutputatclkTrace acquisition complete.
afvalidsOutputatclkATB data flush request for the master port.
atreadysOutputatclkATB transfer ready on slave port.
flushinack OutputatclkFlush input acknowledgement.
fullOutputatclkThe cxetb RAM overflowed or wrapped around.
mbistdout[31:0]OutputatclkMemory BIST data out.
prdatadbg[31:0]OutputpclkdbgDebug APB read data bus.
preadydbgOutputpclkdbgDebug APB ready signal. Use this signal to extend an APB transfer.
triginackOutputatclkTrigger input acknowledgement.

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