A.6.1. Trace Port Interface Unit signals

Table A.32 shows the TPIU signals.

Table A.32. TPIU signals

nameTypeclock domainDescription
afreadys InputatclkATB data flush complete for the master port.
atbytess[1:0]InputatclkATB number of valid bytes, LSB aligned, on the slave port.
atclk InputatclkATB clock.
atclken InputatclkATB clock enable.
atdatas[31:0] InputatclkATB trace data on the slave port.
atids[6:0] InputatclkATB ID for current trace data on slave port.
atresetnInputatclkATB reset for the atclk domain.
atvalids InputatclkATB valid signals present on slave port.
extctlin[7:0] InputatclkExternal control input.
flushin InputatclkFlush input from the CTI.
paddrdbg[11:2] InputpclkdbgDebug APB address bus.
paddrdbg31 InputpclkdbgEnables components to distinguish between internal accesses from system software and external accesses from a debugger.
pclkdbg InputpclkdbgDebug APB clock.
pclkendbg InputpclkdbgDebug APB clock enable.
penabledbg InputpclkdbgDebug APB enable signal, indicates second and subsequent cycles.
presetdbgn InputpclkdbgDebug APB asynchronous reset.
pseldbg InputpclkdbgDebug APB component select.
pwdatadbg[31:0] InputpclkdbgDebug APB write data bus.
pwritedbg InputpclkdbgDebug APB write transfer.
seInputN/AScan enable.
tpctlInputatclkTie-off to report presence of tracectl, static value.
tpmaxdatasize[4:0]InputatclkTie-off to report maximum number of pins on tracedata, static value.
traceclkin InputtraceclkinTrace clock.
tresetn InputtraceclkinTrace clock asynchronous reset.
trigin InputatclkTrigger input from the CTI.
afvalids OutputatclkATB data flush request for the master port.
atreadys OutputatclkATB transfer ready on slave port.
extctlout[7:0] OutputatclkExternal control output.
flushinack OutputatclkFlush input acknowledgement.
prdatadbg[31:0] OutputpclkdbgDebug APB read data bus.
preadydbgOutputpclkdbgDebug APB ready signal.
traceclk OutputtraceclkinHalf the frequency of the exported trace port clock, traceclkin.
tracectlOutputtraceclkinTrace port control.
tracedata[31:0] OutputtraceclkinTrace port data.
triginack OutputatclkTrigger input acknowledgement.

Copyright © 2011-2013, 2015 ARM. All rights reserved.ARM DDI 0480G
Non-ConfidentialID042315