8.4.1. Clocks and resets

The clock and reset signals of the event asynchronous bridge are:

clks

Slave interface clock.

resetsn

Slave interface active-LOW reset. This is asynchronously asserted and must be synchronously deasserted.

clkens

Slave interface clock enable.

clkm

Master interface clock.

resetmn

Master interface active-LOW reset. This is asynchronously asserted and must be synchronously deasserted.

clkenm

Master interface clock enable.

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