11.1.2. Functional interfaces

This component has an APB3-compliant slave interface and CPWRUP master interfaces.

CPWRUP interface

The CPWRUP interface is an asynchronous request and acknowledge interface that enables a requester to communicate with a power controller through a 4-phase handshake mechanism.

Memory-mapped registers in the cxgpr control the CPWRUP interface ports.The cxgpr has hardware logic that enforces the appropriate protocol for the 4-phase handshake.

cx gpr programming interface

The cxgpr has 4KB memory map footprint and contains CoreSight management registers. See Additional reading. The DEVTYPE Register of cxgpr returns 0x34 on a read operation to indicate that it is a power requester block. This value is derived from the register fields:

  • MAJOR = 0x4, meaning Debug Control.

  • SUB = 0x3, meaning Debug Power Requestor.

The APB interface supports zero-wait-state write operations and single-wait-state read operations on the APB.

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