A.1.2. DAPBUS interconnect signals

Table A.2 shows the DAPBUS interconnect signals.

Table A.2. DAPBUS interconnect signals

Name

Type

Clock domain

Description

clk

Input

clk

DAP Clock.

resetn

Input

clk

DAP Reset.

daprdatam31<x>[31:0]

Input

clk

DAP read data bus.

dapreadym<x>

Input

clk

DAP ready.

dapslverrm<x>

Input

clk

DAP error.

dapcaddrs[15:2]

Input

clk

DAP compressed address bus.

dapsels

Input

clk

DAP select.

dapenables

Input

clk

DAP enable.

dapwrites

Input

clk

DAP write or read.

dapwdatas[31:0]

Input

clk

DAP write data bus.

dapaborts

Input

clk

DAP abort.

dapcaddrm<x>[7:2]

Output

clk

DAP compressed address bus.

dapselm<x>

Output

clk

DAP select.

dapenablem<x>

Output

clk

DAP enable.

dapwritem<x>

Output

clk

DAP write or read.

dapwdatam<x>[31:0]

Output

clk

DAP write data bus.

dapabortm<x>

Output

clk

DAP abort.

daprdatas[31:0]

Output

clk

DAP read data bus.

dapreadys

Output

clk

DAP ready.

dapslverrs

Output

clk

DAP error.

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