8.3.1. Clocks and resets

The clock and reset signals of the CTM are:




Active-LOW reset. This is asynchronously asserted and must be synchronously deasserted.


Clock enable.

ARM recommends that the CTM clock runs at the rate of the fastest CTI that it is connected to, to minimize the event signaling issues described in Event signaling protocol.

The CTM includes configurable synchronizers to enable each channel interface to connect to a CTI or CTM in a different clock domain. For more information on configuring these features, see the ARM® CoreSight™ SoC-400 Integration Manual.

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