A.4.4. Narrow timestamp asynchronous bridge signals

Table A.24 shows the narrow timestamp asynchronous bridge signals.

Table A.24. Narrow timestamp asynchronous bridge signals

Name

Type

Clock domain

Description

clkm

Input

clkm

Clock.

resetmn

Input

clkm

Reset.

clks

Input

clks

Clock.

resetsn

Input

clks

Reset.

tsbits[6:0]

Input

clks

Timestamp encoded value.

tssyncs[1:0]

Input

clks

Timestamp synchronization bits.

csysreq[a]

Input

clks

Clock powerdown request.

tssyncreadym

Input

clkm

Timestamp slave ready.

tssyncreadys

Output

clks

Timestamp slave ready.

csysack[a]

Output

clks

Clock powerdown acknowledge.

cactive[a]

Output

clks

Clock is required when driven HIGH.

tsbitm[6:0]

Output

clkm

Timestamp encoded value.

tssyncm[1:0]

Output

clkm

Timestamp synchronization bits.

[a] This signal is only present if you configure the device to have an LPI.


Cross-domain connections

The narrow timestamp asynchronous bridge can be configured as a separate master interface component and slave interface component. If you configure the bridge in this way, then you must connect the two components as Table A.25 shows.

Table A.25 shows narrow timestamp asynchronous bridge cross-domain connections.

Table A.25. Narrow timestamp asynchronous bridge cross-domain connections

Slave component signal TypeMaster component signalType
wr_ptr_gry_sOutputwr_ptr_gry_mInput
encd_data_sOutputend_data_mInput
rd_ptr_gry_sInputrd_ptr_gry_m Output
rd_ptr_bin_sInputrd_ptr_bin_mOutput
lp_req_s Outputlp_req_m Input
lp_ack_s Inputlp_ack_m Output

Copyright © 2011-2013, 2015 ARM. All rights reserved.ARM DDI 0480G
Non-ConfidentialID042315