9.4.5. Off-chip based traceclkin

CoreSight-aware TPAs can optionally directly control a clock source for the trace out port. By running through a known sequence of patterns, from the pattern generator within the TPIU, a TPA can automatically establish the port width and ramp up the clock speed until the patterns degrade, thereby establishing a maximum data rate. Figure 9.1 shows how to generate an off-chip traceclkin.

Figure 9.1. Externally derived traceclk

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The off-chip clock can operate in a similar way to the currently exported traceclk. For example, an externally derived clock source can be double clocked to enable the exported data to change at both edges of the clock.

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