4.1. About the Debug Access Port

The DAP is a collection of components through which off-chip debug tools access a SoC. It is an implementation of the ARM® Debug Interface Architecture Specification, ADIv5.0 to ADIv5.2.

The DAP consists of the following components:

The APs provide non-invasive access to:

Also, some CoreSight-enabled processors connect directly to the DAPBUS interconnect and implement their own ADIv5 compliant AP.

Figure 4.1. Structure of the CoreSight SoC-400 DAP components

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CoreSight SoC has a single multi-function DP as follows:


This is a combined debug port that can communicate in either JTAG or Serial Wire protocols as defined by ADIv5.1. It contains two debug ports, the SW-DP and the JTAG-DP, that you can select through an interface sequence to move between debug port interfaces.

The JTAG-DP is compliant with DP architecture version 0. The SW-DP is compliant with DP architecture version 2 and Serial Wire protocol version 2, that enables a SW-DP to share a target connection with other SW-DPs or other components implementing different protocols.

The access ports included in CoreSight SoC are:


The AXI-AP implements the ADIv5 Memory Access Port (MEM-AP) architecture to directly connect to an AXI memory system. You can connect it to other memory systems using a suitable bridging component.


The AHB-AP provides an AHB-Lite master for access to a system AHB bus. This is compliant with the MEM-AP in ADIv5.1 and can perform 8 to 32-bit accesses.


The APB-AP provides an APB master in AMBA v3.0 for access to the Debug APB bus. This is compliant with the MEM-AP architecture with a fixed transfer size of 32 bits.


The JTAG-AP provides JTAG access to on-chip components, operating as a JTAG master port to drive JTAG chains throughout the ASIC. This is an implementation of the JTAG-AP in ADIv5.1.

The DAPBUS interconnect connects the DP to the APs. A system might not include some types of AP, or it might include more than one of the same type of AP.

Certain processors implement their own Access Port, and these connect directly to the DAPBUS interconnect using the same interface as any other AP. In some documentation this is referred to as an Auxiliary Access Port (AUX-AP) connection.

A DAPBUS asynchronous bridge and a DAPBUS synchronous bridge are provided to enable APs to be implemented in a different clock or power domain to the SWJ-DP.

The ROM table provides a list of memory locations of the CoreSight SoC-400 components that are connected to the debug APB. The ROM table is embedded within the APB interconnect. This is visible from both tools and on-chip self-hosted access. The ROM table indicates the position of all CoreSight SoC-400 components in a system and assists in topology detection. For information about the ROM table, see APB Interconnect with ROM table.

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