10.2. Clocks and resets

The clock and reset signals of the ETB are:

atclk

ATB interface clock. This is the main clock for the ETB, and is used to drive the RAM.

atclken

ATB interface clock enable.

atresetn

ATB interface active LOW reset. This is asynchronously asserted and must be synchronously deasserted.

pclkdbg

APB interface clock.

pclkendbg

APB interface clock enable

presetdbgn

APB interface active LOW reset. This is asynchronously asserted and must be synchronously deasserted.

The ETBrequires the atclk and pclkdbg clocks to be synchronous, that is, clock tree balanced, with respect to each other. pclkdbg must be equivalent to, or an integer division of, atclk. If the pclkendbg and atclken clock enable inputs are used to change the effective update rate of the flip-flops in the ETB then for each enabled pclkdbg edge, that is when pclkendbg = 1, there must be a corresponding enabled atclk edge.

An external asynchronous bridge can be used to bridge to an asynchronous domain if required.

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