A.3.3. ATB upsizer signals

Table A.16 shows the ATB upsizer signals.

Table A.16. ATB upsizer signals

Signal

Type

Clock domain

Description

clk

Input

clkGlobal ATB clock.

resetn

Input

clk

ATB interface reset when LOW. This signal is asserted LOW asynchronously, and deasserted HIGH synchronously.

atids[6:0]

Input

clkAn ID that uniquely identifies the source of the trace.

atvalids

Input

clkA transfer is valid during this cycle. If LOW, all other ATB signals must be ignored in this cycle.

atbytess[<sbw>:0][a]

Input

clkThe number of bytes on atdata to be captured, minus 1.

atdatas[<sdw>:0][b]

Input

clkTrace data.

afreadys

Input

clkThis is a flush acknowledge. Asserted when buffers are flushed.

atreadym

Input

clkSlave is ready to accept data.

afvalidm

Input

clkThis is the flush signal. All buffers must be flushed because trace capture is about to stop.
syncreqmInputclkSynchronization request.

atreadys

Output

clkSlave is ready to accept data.
afvalidsOutputclkThis is the flush signal. All buffers must be flushed because trace capture is about to stop.
syncreqsOutputclkSynchronization request.

atvalidm

Output

clkA transfer is valid during this cycle. If LOW, all the other ATB signals must be ignored in this cycle.

atidm[6:0]

Output

clkAn ID that uniquely identifies the source of the trace.

atbytesm[<mbw>:0][c]

Output

clkThe number of bytes on atdata to be captured, minus 1.

atdatam[<mdw>:0][d]

Output

clkTrace data.

afreadym

Output

clkThis is a flush acknowledge. Asserted when buffers are flushed.

[a] <sbw> has a range of 0-2.

[b] <sdw> value can be either 7, 15, 31, or 63.

[c] <mbw> has a range of 0-3.

[d] <mdw> value can be either 7, 15, 31, 62, or 127.


Copyright © 2011-2013, 2015 ARM. All rights reserved.ARM DDI 0480G
Non-ConfidentialID042315