3.13.7. Current Test Pattern/Modes register

The Current_test_pattern_mode register characteristics are:

Purpose

Indicates the current test pattern or mode selected. Only one of the modes can be set, using bits[17:16], but a multiple number of bits for the patterns can be set using bits[3:0]. When timed mode is selected, after the allotted number of cycles is reached, the mode automatically switches to off mode. On reset, this register is set to 18'h00000 that indicates the off mode with no selected patterns.

Usage constraints

There are no usage constraints.

Configurations

This register is available in all configurations.

Attributes

See the register summary in Table 3.114.

Figure 3.113 shows the bit assignments.

Figure 3.113. Current_test_pattern_mode register bit assignments

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Table 3.121 shows the bit assignments.

Table 3.121. Current_test_pattern_mode register bit assignments

BitsNameFunction
[31:18]Reserved

-

[17]PCONTEN

Indicates whether Continuous Mode is enabled.

0

Mode disabled.

1

Mode enabled.

[16]PTIMEEN

Indicates whether Timed Mode is enabled.

0

Mode disabled.

1

Mode enabled.

[15:4]Reserved

-

[3]PATF0

Indicates whether the FF/00 pattern is enabled as output over the Trace Port.

0

Pattern disabled.

1

Pattern enabled.

[2]PATA5

Indicates whether the AA/55 pattern is enabled as output over the Trace Port.

0

Pattern disabled.

1

Pattern enabled.

[1]PATW0

Indicates whether the walking 0s pattern is enabled as output over the Trace Port.

0

Pattern disabled.

1

Pattern enabled.

[0]PATW1

Indicates whether the walking 1s pattern is enabled as output over the Trace Port.

0

Pattern disabled.

1

Pattern enabled.


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