A.3.1. ATB replicator signals

Table A.14 shows the ATB replicator signals.

Table A.14. ATB replicator signals

Name TypeClock domainDescription
afreadysInputclkATB data flush complete on the slave port.
afvalidm0 InputclkATB data flush request on the master port 0.
afvalidm1 InputclkATB data flush request on the master port 1.
atbytess[<bw>:0] [a]InputclkATB number of valid bytes, LSB aligned, on the slave port.
clk InputclkATB clock.
atdatas[<dw>:0] [b]InputclkATB trace data.
atids[6:0] InputclkATB ID for current trace data.
atreadym0 InputclkATB transfer ready on master port 0.
atreadym1 InputclkATB transfer ready on master port 1.
resetnInputclkATB reset.
atvalidsInputclkATB valid signal present.
paddrdbg[11:2] InputclkDebug APB address bus.
penabledbg InputclkDebug APB enable signal, indicates second and subsequent cycles.
pseldbg InputclkDebug APB component select.
pwdatadbg[31:0] InputclkDebug APB write data bus.
pwritedbg InputclkDebug APB write transfer.
pclkendbgInputclkDebug APB clock enable.
paddrdbg31 InputclkEnables components to distinguish between internal accesses from system software, and external accesses from a debugger.
syncreqm0InputclkSynchronization request.
syncreqm1InputclkSynchronization request.
afreadym0OutputclkATB data flush complete for the master port 0.
afreadym1OutputclkATB data flush complete for the master port 1.
afvalidsOutputclkATB data flush request for the master port.
atbytesm0[<bw>:0] [b]OutputclkATB number of valid bytes, LSB aligned, on the master port.
atbytesm1[<bw>:0] [b]OutputclkATB number of valid bytes, LSB aligned, on the master port.
atdatam0[<dw>:0][c]OutputclkATB trace data on the master port 0.
atdatam1[<dw>:0][c]OutputclkATB trace data on the master port 1.
atidm0[6:0] OutputclkATB ID for current trace data on master port 0.
atidm1[6:0] OutputclkATB ID for current trace data on master port 1.
atreadysOutputclkATB transfer ready.
atvalidm0 OutputclkATB valid signal present on master port 0.
atvalidm1 OutputclkATB valid signal present on master port 1.
preadydbgOutputclkDebug APB ready signal.
prdatadbg[31:0]OutputclkDebug APB read data bus.
pslverrdbgOutputclkDebug APB transfer error signal.
syncreqsOutputclkSynchronization request.

[a] <bw> has a value in the range 0-3 that is calculated at configuration time.

[b] <dw> is the width of the data bus minus one.


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