3.3.9. Device Architecture register

The DEVARCH register characteristics are:

Purpose

Returns the device architecture identifier value.

Usage constraints

There are no usage constraints.

Configurations

This register is available in all configurations.

Attributes

See the register summary in Table 3.1.

Figure 3.7 shows the bit assignments.

Figure 3.7. DEVARCH register bit assignments

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Table 3.10 shows the bit assignments.

Table 3.10. DEVARCH register bit assignments

BitsNameDescription
[31:21]ARCHITECT

Indicates the component architect:

0x23B

ARM.

[20]PRESENT

Indicates whether the DEVARCH register is present:

0x1

Present.

[19:16]REVISION

Indicates the architecture revision:

0x1

Revision 0.

[15:0]ARCHID

Indicates the component:

0x0A34

CoreSight GPR.


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