5.1.3. Device operation

This section describes device operation in the following subsections:

Accesses to ROM table

Accesses to addresses in the range 0x0000 - 0x0FFC are decoded to the ROM table. See the ARM® Debug Interface Architecture Specification, ADIv5.0 to ADIv5.2 for information on ROM tables.

Arbitration

The internal arbiter arbitrates between competing slave interfaces for access to debug APB as the following algorithm demonstrates:

  • When a slave interface raises a request, the highest priority is given to the slave interface with the lowest instance suffix, that is, SlvIntf0 > SlvIntf1 > SlvIntf2 > … > SlvIntf(n-1). The order in which these slave interfaces raised their requests relative to each other is not used in arbitration.

  • The arbitration is re-evaluated after every access.

Error response

The APB interconnect returns an error on its slave interface under any of the following conditions:

  • The targeted debug APB device returns an error response.

  • The address accessed by a slave interface does not decode to any debug APB device.

  • A system access is attempted to a debug APB device when not permitted. This occurs when the DbgSwEnable bit in the APB-AP is cleared, and self-hosted, on-chip, accesses are attempted.

Address width on master interfaces

The width of the address bus on the master interface depends on the size of the address space allocated to that interface through bit[31] of the address bus. Bit[31] is always exported onto the master interface. Table 5.1 shows the address bus widths for each setting of size.

Table 5.1. Address bus on the master interfaces

Size of address space

Address bus on the master interface,

where x=0 to NUM_MASTER_INTF-1

4KBpaddrm<x>[11:2]
8KBpaddrm<x>[12:2]
16 KBpaddrm<x>[13:2]
32 KBpaddrm<x>[14:2]
64 KBpaddrm<x>[15:2]
128 KBpaddrm<x>[16:2]
256 KBpaddrm<x>[17:2]
512 KBpaddrm<x>[18:2]
1 MBpaddrm<x>[19:2]
2 MBpaddrm<x>[20:2]
4 MBpaddrm<x>[21:2]
8 MBpaddrm<x>[22:2]
16 MBpaddrm<x>[23:2]
32 MBpaddrm<x>[24:2]
64 MBpaddrm<x>[25:2]
128 MBpaddrm<x>[26:2]
256 MBpaddrm<x>[27:2]
512 MBpaddrm<x>[28:2]
1 GBpaddrm<x>[29:2]

Note

<x> is the master interface number, from 0 to NUM_MASTER_INTF - 1. Master port base addresses must be aligned to their size.

Address width on slave interfaces

The address width on the APB slave interfaces depends on the total memory footprint occupied by the defined master interfaces and the 4KB footprint of the ROM Table.

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