A.1.3. DAPBUS asynchronous bridge signals

Table A.3 shows the DAPBUS asynchronous bridge signals.

Table A.3. DAPBUS asynchronous bridge signals

Signal

Type

Clock domain

Description

dapclks

Input

dapclksDAP clock.
dapclkensInputdapclksDAP clock enable.

dapresetsn

Input

dapclksDAP reset.
dapclkenmInputdapclksDAP clock enable.

dapclkm

Input

dapclkmDAP clock.

dapresetm

Input

dapclksDAP reset.
dapselsInputdapclksThe DAP select signal. Indicates that the DAP bus master is selecting this slave device and requires a data transfer.
dapabortsInputdapclksThe DAP abort. When the bus master asserts dapaborts HIGH, the DAP slave aborts the present DAP transfer and asserts dapreadys HIGH in the next cycle.
dapenablesInputdapclksThe DAP enable. Indicates the second and subsequent cycles of a DAP transfer.
dapwritesInputdapclksThe DAP RW select signal. It indicates a DAP write access when HIGH and a DAP read access when LOW.
dapaddrs[31:0]InputdapclksThe DAP address bus.
dapwdatas[31:0]InputdapclksThe DAP write data bus.
dapreadymInputdapclkmThe DAP ready. The slave indicates whether it has completed present transfer and is ready for the next transfer.
dapslverrmInputdapclkmThe DAP slave error. The slave indicates that the present transfer has a error.
daprdatam[31:0]InputdapclkmThe DAP read data. The read data of the present DAP read transfer.
csysreq[a]InputdapclksClock powerdown request.
dapreadysOutputdapclksThe DAP ready. The DAP bus slave asserts this signal HIGH to indicate that it completed the current DAP transfer and is ready for the next transfer.
dapslverrsOutputdapclksThe DAP slave error. When HIGH, the DAP slave indicates that the present DAP transaction had an error.
daprdatas[31:0]OutputdapclksThe DAP read data. Carries the read data of a DAP read transfer.
dapselmOutputdapclkmThe DAP select. Indicates that the master is selecting a particular slave for RW transfer.
dapabortmOutputdapclkmThe DAP abort. When asserted HIGH, it indicates that the master is aborting the present transaction.
dapenablemOutputdapclkmThe DAP enable. Indicates the second and subsequent cycles of a DAP transfer.
dapwritemOutputdapclkmThe DAP RW. Indicates a write transfer when HIGH and a read transfer when LOW.
dapaddrm[31:0]OutputdapclkmThe DAP address bus.
dapwdatam[31:0]OutputdapclkmThe DAP write data. The master drives this bus and carries the write data for the present write transfer.
csysack[a]OutputdapclksClock powerdown acknowledge.
cactive[a]OutputdapclksClock is required when driven HIGH.

[a] This signal is only present if you configure this component to have an LPI.


Cross-domain connections

The DAPBUS asynchronous bridge can be configured as a separate master interface component and slave interface component. If you configure the bridge in this way, then you must connect the two components as Table A.4 shows.

Table A.4 shows DAPBUS asynchronous bridge cross-domain connections

Table A.4. DAPBUS asynchronous bridge cross-domain connections

Slave component signal TypeMaster component signalType
dapm_req_asyncOutput daps_req_asyncInput
dapm_ack_async Input daps_ack_async Output
dapm_fwd_data_async Output daps_fwd_data_async Input
dapm_rev_data_async Input daps_rev_data_async Output
dapm_abort_req_async Outputdaps_abort_req_async Input

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