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Home > Debug Access Port > AHB-AP > External interfaces |
The primary external interface to the system is an AHB-Lite master port that supports:
AHB in AMBA v2.0.
ARM11 AMBA extensions.
TrustZone extensions.
The AHB-Lite master port does not support:
BURST and SEQ.
Exclusive accesses.
Unaligned transfers.
Table 4.8 shows the other AHB-AP ports.
Table 4.8. Other AHB-AP ports
Name | Type | Description |
---|---|---|
dbgen | Input | Enables AHB-AP transfers if HIGH. Access to the AHB-AP registers is still permitted if dbgen is LOW, but no AHB transfers are initiated. If a transfer is attempted when dbgen is LOW, then the DAP bus returns dapslverr HIGH. |
spiden | Input | Permits Secure transfers to take place on the AHB-AP. If spiden is HIGH, then hprot[6] can be asserted as programmed into the SProt bit in the CSW Register. See Chapter 3 Programmers Model. |
hprot[6:0] is provided as an external port and is programmed from the Prot field in the CSW register with the following conditions:
hprot[4:0] programming is supported.
hprot[5] is not programmable and is always LOW. Exclusive access is not supported, and therefore hprot[2] is not supported.
hprot[6] programming is supported. hprot[6] HIGH is a Non-secure transfer. hprot[6] LOW is a Secure transfer. hprot[6] can be asserted LOW by writing to the SProt field in the CSW Register. A Secure transfer can only be initiated if spiden is HIGH. If SProt is set LOW in the CSW Register to perform a Secure transfer, but spiden is LOW, then no AHB transfer takes place.
See Chapter 3 Programmers Model for values of the Prot field.
hresp[0] is the only RESPONSE signal that the AHB-AP requires:
AHB-Lite
devices do not support SPLIT and RETRY and therefore hresp[1] is not required. It is still
provided as an input, and if not present on any slave it must be
tied LOW. Any hresp[1:0] response
that is not 0b00
, OKAY, is treated as an ERROR
response.
hresp[2] is not required because exclusive accesses are not supported in the AHB-AP.
hbstrb[3:0] signals are automatically generated based on the transfer size hsize[2:0] and haddr[1:0]. Byte, half-word, and word transfers are supported. It is not possible for you to directly control hbstrb[3:0].
Unaligned transfers are not supported. Table 4.9 shows an example of the generated hbstrb[3:0] signals for different-sized transfers.
Table 4.9. Example generation of byte lane strobes
Transfer description | haddr[1:0] | hsize[2:0] | hbstrb[3:0] |
---|---|---|---|
8-bit access to 0x1000 | 0b00 | 0b000 | 0b0001 |
8-bit access to 0x1003 | 0b11 | 0b000 | 0b1000 |
16-bit access to 0x1002 | 0b10 | 0b001 | 0b1100 |
32-bit access to 0x1004 | 0b00 | 0b010 | 0b1111 |
The AHB-AP cannot initiate a new AHB transfer every clock cycle because of the additional cycles required to serial scan in the new address or data value through a debug port. The AHB-AP supports two htrans transfer types, IDLE and NONSEQ:
When a transfer is in progress, it is of type NONSEQ.
When no transfer is in progress and the AHB-AP is still granted the bus, the transfer is of type IDLE.
The only unpacked hburst encoding supported is SINGLE. Packed 8-bit transfers or 16-bit transfers are treated as individual NONSEQ, SINGLE transfers at the AHB-Lite interface. This ensures that there are no issues with boundary wrapping, to avoid additional AHB-AP complexity.
A full AHB master interface can be created by adding an AHB-Lite to AHB wrapper to the output of the AHB-AP, as provided in the AMBA Design Kit.