3.17.2. AHB-AP register descriptions

This section describes the registers used to program the AHB-AP. It contains the following registers:

AHB-AP Control/Status Word register, CSW, 0x00

Purpose

Configures and controls transfers through the AHB interface.

Attributes

Figure 3.199 shows the bit assignments.

Figure 3.199. AHB-AP CSW register bit assignments

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Table 3.214 shows the bit assignments.

Table 3.214. AHB-AP Control/Status Word register bit assignments

BitsTypeNameFunction
[31]--Reserved SBZ.
[30]RWSProt

Specifies that a Secure transfer is requested.

SProt HIGH indicates a Non-secure transfer. SProt LOW indicates a Secure transfer.

  • If this bit is LOW, and spiden is HIGH, hprot[6] is asserted LOW on an AHB transfer.

  • If this bit is LOW, and spiden is LOW, hprot[6] is asserted HIGH and the AHB transfer is not initiated.

  • If this bit is HIGH, the state of spiden is ignored. hprot[6] is HIGH.

The reset value is 1.

This field is Non-secure.

[29]--Reserved, SBZ.
[28:24]RWProt

Specifies the protection signal encoding to be output on hprot[4:0].

The reset value is 0b00011.

This field is Non-secure, non-exclusive, non-cacheable, non-bufferable, and privileged.

[23]ROSPIStatusIndicates the status of the spiden port. If SPIStatus is LOW, no Secure AHB transfers are carried out.
[22:12]--Reserved, SBZ.
[11:8]RWMode

Specifies the mode of operation.

0b0000

Normal download or upload model.

0b0001-0b1111

Reserved, SBZ.

The reset value is 0b0000.

[7]ROTrInProgTransfer in progress. This field indicates whether a transfer is currently in progress on the AHB master port.
[6]RODbgStatus

Indicates the status of the dbgen port. If DbgStatus is LOW, no AHB transfers are carried out.

1

AHB transfers permitted.

0

AHB transfers not permitted.

[5:4]RWAddrInc

Auto address increment and packing mode on RW data access. Only increments if the current transaction completes without an error response and the transaction is not aborted.

Auto address incrementing and packed transfers are not performed on access to Banked Data registers, 0x10-0x1C. The status of these bits is ignored in these cases.

Incrementing and wrapping is performed within a 1KB address boundary, for example, for word incrementing from 0x1400-0x17FC. If the start is at 0x14A0, then the counter increments to 0x17FC, wraps to 0x1400, then continues incrementing to 0x149C.

0b00

Auto increment OFF.

0b00

Increment, single.

Single transfer from corresponding byte lane.

0b10

Increment, packed.

Word

Same effect as single increment.

Byte or halfword

Packs four 8-bit transfers or two 16-bit transfers into a 32-bit DAP transfer. Multiple transactions are carried out on the AHB interface.

0b11

Reserved, SBZ. No transfer.

Size of address increment is defined by the Size field, bits [2:0].

The reset value is 0b00.

[3]RW-

Reserved, SBZ.

The reset value is 0.

[2:0]RWSize

Size of the data access to perform.

0b000

8 bits.

0b001

16 bits.

0b010

32 bits.

0b011- 0b111

Reserved, SBZ.

The reset value is 0b010.


AHB-AP Transfer Address Register, TAR, 0x04

Table 3.215 shows the bit assignments.

Table 3.215. AHB-AP Transfer Address register bit assignments

BitsTypeNameFunction
[31:0]RWAddress

Address of the current transfer.

The reset value is 0x00000000.


AHB-AP Data Read/Write register, DRW, 0x0C

Table 3.216 shows the bit assignments.

Table 3.216. AHB-AP Data Read/Write register bit assignments

BitsTypeNameFunction
[31:0]RWData
Write mode

Data value to write for the current transfer.

Read mode

Data value that is read from the current transfer.


AHB-AP Banked Data registers, BD0-BD03, 0x10-0x1C

Purpose

BD0-BD3 provide a mechanism for directly mapping through DAP accesses to AHB transfers without having to rewrite the TAR within a four-location boundary. BD0 is RW from TA. BD1 is RW from TA+4.

Attributes

Table 3.217 shows the bit assignments.

Table 3.217. Banked Data register bit assignments

BitsTypeNameFunction
[31:0]RWData

If dapcaddr[7:4] = 0x0001, it is accessing AHB-AP registers in the range 0x10-0x1C, and the derived haddr[31:0] is:

Write mode

Data value to write for the current transfer to external address TAR[31:4] + dapcaddr[3:2] + 0b00.

Read mode

Data value that is read from the current transfer from external address TAR[31:4] + dapcaddr[3:2] + 0b00.

Auto address incrementing is not performed on DAP accesses to BD0-BD3.

Banked transfers are only supported for word transfers. Non-word banked transfers are reserved and unpredictable. Transfer size is currently ignored for banked transfers.


AHB-AP Debug Base Address register, ROMBASE, 0xF8

Table 3.218 shows the bit assignments.

Table 3.218. AHB-AP Debug Base Address register bit assignments

BitsTypeNameFunction
[31:0]RODebug AHB ROM Base Address

Base address of a ROM table. Bit[1] is always 1, and the other bits are set to the tie-off value on the static input port, rombaseaddr.

The ROM provides a look-up table for system components.

Set bit[0] to 1 if there are debug components on this bus.


AHB-AP Identification Register, IDR, 0xFC

Figure 3.200 shows the bit assignments.

Figure 3.200. AHB-AP Identification Register bit assignments

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Table 3.219 shows the bit assignments.

Table 3.219. AHB-AP Identification Register bit assignments

BitsTypeNameValueFunction
[31:28]RORevision0x8r0p9
[27:24]ROJEDEC bank0x4Designed by ARM
[23:17]ROJEDEC code0x3BDesigned by ARM
[16]ROMem AP0x1Is a Mem AP
[15:8]-Reserved0x00-
[7:0]ROIdentity value0x01AHB-AP

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