A.2.1. APB interconnect signals

Table A.10 shows the APB interconnect signals.

Table A.10. APB interconnect signals

Signal

Type

Clock domain

Description

clk

Input

clkThe clock reference signal for all APB debug interfaces. The rising edge of clk times all transfers on the APB.

resetn

Input

clkActive-LOW reset.

prdatam<x>[31:0][c]

Input

clkAPB read data. Drives this bus during read cycles.

preadym<x>[c]

Input

clkAPB ready. Uses this signal to extend an APB transfer.

pslverrm<x>[c]

Input

clkIndicates a transfer failure. The APB peripherals are not required to support the pslverr pin.

paddrs<x>[saw:2][a][b]

Input

clkThe APB address bus for slave interface <x>.

psels<x>[a]

Input

clkSelect. Indicates that the slave interface <x> is selected, and a data transfer is required.

penables<x>[a]

Input

clkEnable. Indicates the second and subsequent cycles of an APB transfer initiated on slave interface <x>.

pwrites<x>[a]

Input

clkDirection. Indicates an APB write access when HIGH and an APB read access when LOW.

pwdatas<x>[31:0][a]

Input

clkWrite data that the APB master device connected to the APBIC slave interface <x> drives.
targetid[31:0]Inputclk

Provides information to uniquely identify the sub system connected to this APBIC.

paddr31s0

Input

clkEnables components to distinguish between internal accesses from system software, and external accesses from a debugger.
dbgswenInputclkEnable software access to debug APB.

paddrm<x>[maw:2][c][d]

Output

clkThe APB address bus for master interface <x>.

pselm<x>[c]

Output

clkAPB select. Indicates that the slave device connected to master interface <x> is selected, and a data transfer is required.

penablem<x>[c]

Output

clkAPB enable. Indicates the second and subsequent cycles of an APB transfer that the master interface <x> initiates.

pwritem<x>[c]

Output

clkAPB RW transfer. Indicates an APB write access when HIGH, and an APB read access when LOW.

pwdatam<x>[31:0][c]

Output

clkWrite data that the APBIC master interface <x> drives.

prdatas<x>[31:0][a]

Output

clkRead data. The slave interface <x> drives this bus during read cycles.

preadys<x>[a]

Output

clkAPB ready. The slave interface <x> uses this signal to extend an APB transfer.

pslverrs<x>[a]

Output

clkIndicates a transfer failure.

[a] Where <x>=0 to (NUM_SLAVE_INTF-1).

[b] Where saw is a parameter dependent number.

[c] Where <x>=0 to (NUM_MASTER_INTF-1).

[d] Where maw is a parameter dependent number.


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