4.7.7. Packed transfers

The DAPBUS interface is a 32-bit data bus. However, 8-bit or 16-bit transfers can be formed on AXI according to the size field in the CSW register, 0x000. The AddrInc field in the CSW Register permits optimized use of DAPBUS to reduce the number of accesses to the DAP. It indicates whether the entire data word can be used to pack more than one transfer. If packed transfers are initiated, then address incrementing is automatically enabled. Multiple transfers are carried out in sequential addresses, with the size of the address increment based on the size of the transfer.

Examples of the transactions are:

For an unpacked 16-bit write at a base address of base 0x2, that is, CSW[2:0] = 0b001, CSW[5:4] = 0b01, WDATA[31:16] is written from bits [31:16] in the DRW register.

For an unpacked 8-bit read at a base address of base 0x1, that is, CSW[2:0] = 0b000, CSW[5:4] = 0b01, RDATA[31:16] and RDATA[7:0] are zero, RDATA[15:8] contains read data.

For a packed byte write at base address of base 0x2, that is, CSW[2:0] = 0b000 and CSW[5:4] = 0b10, four write transfers are initiated, and the order of data that is sent is:

For a packed half-word read at a base address of base 0x2, that is, CSW[2:0] = 0b001, CSW[5:4] = 0b10, two read transfers are initiated:

The AXI-AP only asserts DAPREADY HIGH when all packed transfers from the AXI interface have completed.

If the current transfer is aborted or the current transfer receives an ERROR response, the AXI-AP does not complete the subsequent packed transfers and returns DAPREADY HIGH immediately after the current packed transfer.

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