4.7.6. AXI transfers

The AMBA4 AXI compliant Master Port supports the following features:

Burst length

The AXI-AP supports burst length of one transfer only. ARLEN[3:0] and AWLEN[3:0] are always 0b0000.

Packed 8 or 16-bit transfers are treated as individual burst lengths of one transfer at the AXI interface. This ensures that there are no issues with boundary wrapping to avoid additional AXI-AP complexity.

Burst size

Supported burst sizes are:

  • 8-bit.

  • 16-bit.

  • 32-bit.

  • 64-bit.

Burst type

ARBURST and AWBURST signals are always 0b01.

Because only bursts of one transfer are supported, burst type has no meaning in this context.

Atomic accesses

AXI-AP supports normal accesses only.

ARLOCK and AWLOCK signals are always 0b00.

Unaligned accesses

Unaligned accesses are not supported. Depending on the size of the transfers, addresses must be aligned.

  • For 16-bit half word transfers:

    • Base address 0x01 is aligned and AxADDR[7:0] = 0x00.

    • Base address 0x02 is retained and AxADDR[7:0] = 0x02.

  • For 32-bit word transfers:

    • Base address 0x01 to 0x03 is aligned and AxADDR[7:0] = 0x00.

    • Base address 0x04 is retained and AxADDR[7:0] = 0x04.

  • For 64-bit word transfers:

    • Base address 0x04 is aligned and AxADDR[7:0] = 0x00.

    • Base address 0x08 is retained and AxADDR[7:0] = 0x08.

For example, for 16-bit transfers, addresses must be aligned to a 16-bit half-word boundary, for 32-bit word transfers, addresses must be word-aligned, and for 64-bit double-word transfers, addresses must be double-word aligned.

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