ARM CoreSight SoC-400 Technical Reference Manual: 2.1.6. AXI access port

2.1.6. AXI access port

The AXI Access Port (AXI-AP) is an AXI bus master and enables a debugger to issue AXI transactions. You can connect it to other memory systems using a suitable bridging component.

The AXI-AP has the following features:

Supports a single clock domain.
Has a configurable 32-bit or 64-bit address width.
Has a configurable 32-bit or 64-bit data width.
Has AXI4 interface support for the following:
- Large Physical Address Extension (LPAE).
- Burst length of one.
- No out-of-order transactions.
- No multiple outstanding accesses except for barrier transactions.
- No write data interleaving.
- Only aligned transfers.
- No EXCLUSIVE and LOCK transactions.
- No QoS signaling.
Has ACE-Lite support for system coherency as follows:
- ReadOnce and WriteUnique support for shared memory regions.
- ReadNoSnoop and WriteNoSnoop support for non-shared memory regions.
- Synchronization and memory barrier transactions support.
Is little-endian.
Supports error responses.
Supports packed transfers, enabling multiple 8-bit or 16-bit transfers to be issued with a single debugger access to the AXI-AP.

You must configure the AXI-AP during implementation, with the following parameters:

AXI_ADDR_WIDTH, 32-bit or 64-bit.
AXI_DATA_WIDTH, 32-bit or 64-bit.

See Chapter 4 Debug Access Port.

Figure 2.6 shows the external connections on the AXI-AP.

Figure 2.6. AXI Access Port block diagram

Note

aw and dw are calculated automatically from AXI_ADDR_WIDTH and AXI_DATA_WIDTH, respectively, when the rtl is rendered.

Copyright © 2011-2013, 2015 ARM. All rights reserved.	ARM DDI 0480G
Non-Confidential	ID042315
PDF version