2.1.6. AXI access port

The AXI Access Port (AXI-AP) is an AXI bus master and enables a debugger to issue AXI transactions. You can connect it to other memory systems using a suitable bridging component.

The AXI-AP has the following features:

You must configure the AXI-AP during implementation, with the following parameters:

See Chapter 4 Debug Access Port.

Figure 2.6 shows the external connections on the AXI-AP.

Figure 2.6. AXI Access Port block diagram

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Note

aw and dw are calculated automatically from AXI_ADDR_WIDTH and AXI_DATA_WIDTH, respectively, when the rtl is rendered.

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