2.2.1. APB interconnect with ROM table

The APB InterConnect (APBIC) with ROM table connects multiple APB masters to multiple slaves. The APBIC implements a ROM table that contains information about the components in a CoreSight SoC-400 system.

The debug APBIC has the following key features:

The APBIC operates in a single clock domain. Use asynchronous bridges to connect other components that are not synchronous.

Figure 2.9 shows the external connections on the APBIC. <x> in the figure denotes an automatically-generated numeric interface number. The following depend on the configuration:

Figure 2.9. APB interconnect with ROM table block diagram

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Note

saw, the slave port address width, and maw, the master port address width, are calculated automatically from top-level configuration parameters when the rtl is rendered.

For information about the APBIC registers, see Chapter 3 Programmers Model.

Cascading APBICs

Systems that require more than the maximum configurable number of slaves can use a cascading approach. You can connect two or more APBICs to implement a hierarchy of APB peripherals.

For more information on cascading APB interconnects, see the ARM® CoreSight™ SoC-400 Integration Manual.

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