4.6.1. External interfaces

Table 4.4 shows the JTAG to slave device signals.

Each of the eight JTAG scan chains is on the same bit position for each JTAG signal. For example, connections for scan chain 0 can be located on bit [0] of each bus connection of cstck, cstms, cstdi, and portconnected.

Table 4.4. JTAG to slave device signals

nsrstout[7:0]OutputSub system reset out.
srstconnected[7:0]InputSub system reset is present.
ncstrst[7:0]OutputJTAG test reset.
cstck[7:0]OutputJTAG test clock.
cstms[7:0]OutputJTAG test mode select.
cstdi[7:0]OutputJTAG test data in, to external TAP.
cstdo[7:0]InputJTAG test data out, from external TAP.
csrtck[7:0]InputReturn test clock, target pacing signal.
portconnected[7:0]InputJTAG port is connected, status signal.
portenabled[7:0]InputJTAG port is enabled, for example, it might be deasserted by a processor powering down.

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