A.5.1. Cross Trigger Interface signals

Table A.29 shows the CTI signals.

Table A.29. CTI signals

NameTypeClock domainDescription

cihsbypass[3:0]

InputcticlkChannel interface handshake bypass.

cisbypass

InputcticlkChannel interface sync bypass.

ctiapbsbypass

InputcticlkSynchronization bypass between APB and CTI clock.

ctichin[3:0]

InputcticlkChannel in.

ctichoutack[3:0]

InputcticlkChannel out acknowledge.

cticlk

InputcticlkCTI clock.

cticlken

InputcticlkCTI clock enable.

ctitrigin[7:0]

InputcticlkTrigger in.

ctitrigoutack[7:0]

InputcticlkTrigger out acknowledge.

dbgen

InputNAInvasive debug enable.
ctiresetnInputcticlkReset.
niden InputcticlkNon-invasive debug enable.
paddrdbg[11:2]InputpclkdbgDebug APB address bus.
paddrdbg31 InputpclkdbgEnables components to distinguish between internal accesses from system software and external accesses from a debugger.

pclkdbg

InputpclkdbgDebug APB clock.

pclkendbg

InputpclkdbgDebug APB clock enable.

penabledbg

InputpclkdbgDebug APB enable signal, indicates second and subsequent cycles.

presetdbgn

InputpclkdbgDebug APB reset.

pseldbg

InputpclkdbgDebug APB component select.

pwdatadbg[31:0]

InputpclkdbgDebug APB write data bus.

pwritedbg

InputpclkdbgDebug APB write transfer.

se

InputN/AScan enable.

tihsbypass[7:0]

InputcticlkTrigger interface handshake bypass, static value.

tinidensel[7:0]

InputcticlkMasks when NIDEN is LOW, static value.

tisbypassack[7:0]

InputcticlkTrigger out acknowledge sync bypass, static value.

tisbypassin[7:0]

InputcticlkTrigger in sync bypass, static value.

todbgensel[7:0]

InputcticlkMasks when dbgen is LOW, static value.

asicctl[7:0]

OutputcticlkExternal multiplexer control.

ctichinack[3:0]

OutputcticlkChannel in acknowledge.

ctichout[3:0]

OutputcticlkChannel out.

ctitriginack[7:0]

OutputcticlkTrigger in acknowledge.

ctitrigout[7:0]

OutputcticlkTrigger out.

prdatadbg[31:0]

OutputpclkdbgDebug APB read data bus.

preadydbg

OutputpclkdbgDebug APB ready signal.

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