3.5.4. Peripheral ID1 Register

The PIDR1 characteristics are:


Part of the set of peripheral identification registers. Contains part of the designer-specific part number and part of the designer identity.

Usage constraints

There are no usage constraints.


This register is available in all configurations.


See the register summary in Table 3.22.

Figure 3.22 shows the bit assignments.

Figure 3.22. PIDR1 bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

Table 3.26 shows the bit assignments.

Table 3.26. PIDR1 bit assignments




Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component.

Either the targetid[4:1] from the DAP or a sub-system identifier.


Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this part number.

Either the targetid[27:24] from the DAP or a sub-system identifier.

Copyright © 2011-2013, 2015 ARM. All rights reserved.ARM DDI 0480G