6.6.1. Clock and reset

The two synchronous clock domains must use the same clock input. Clock enable inputs are used to indicate the relative speeds of the two clock domains. The ATB synchronous bridge uses the following clock and reset signals:

clk

Clock.

resetn

Active-LOW reset. This is asynchronously asserted and must be synchronously deasserted.

clkens

Clock enable for the slave port.

clkenm

Clock enable for the master port.

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