7.6.2. Clocks and resets

The two synchronous clock domains must use the same clock input. Clock enable inputs are used to indicate the relative speeds of the two clock domains.

The narrow timestamp synchronous bridge uses the following clock and reset signals:

clk

Clock.

resetn

Active-LOW reset. This is asynchronously asserted and must be synchronously deasserted.

clkenm

Clock enable for the master interface.

clkens

Clock enable for the slave interface.

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