ARM® CoreSight™ SoC-400 Technical Reference Manual

Revision: r3p2

Table of Contents

About this book
Product revision status
Intended audience
Using this book
Additional reading
Feedback on this product
Feedback on content
1. Introduction
1.1. About CoreSight SoC-400
1.1.1. Structure of CoreSight SoC-400
1.1.2. CoreSight SoC-400 block summary
1.1.3. Typical CoreSight SoC-400 system
1.2. Compliance
1.3. Features
1.4. Interfaces
1.5. Configurable options
1.6. Test features
1.7. Product documentation and design flow
1.8. Product revisions
2. Functional Overview
2.1. DAP components
2.1.1. Serial Wire or JTAG Debug Port
2.1.2. DAPBUS interconnect
2.1.3. DAPBUS asynchronous bridge
2.1.4. DAPBUS synchronous bridge
2.1.5. JTAG access port
2.1.6. AXI access port
2.1.7. AHB access port
2.1.8. APB access port
2.2. APB components
2.2.1. APB interconnect with ROM table
2.2.2. APB asynchronous bridge
2.2.3. APB synchronous bridge
2.3. ATB interconnect components
2.3.1. ATB replicator
2.3.2. ATB funnel
2.3.3. ATB upsizer
2.3.4. ATB downsizer
2.3.5. ATB asynchronous bridge
2.3.6. ATB synchronous bridge
2.3.7. ATB Phantom Bridges
2.4. Timestamp components
2.4.1. Timestamp generator
2.4.2. Timestamp encoder
2.4.3. Narrow timestamp replicator
2.4.4. Narrow timestamp asynchronous bridge
2.4.5. Narrow timestamp synchronous bridge
2.4.6. Timestamp decoder
2.4.7. Timestamp interpolator
2.5. Embedded Cross Trigger components
2.5.1. Cross Trigger Interface
2.5.2. Cross Trigger Matrix
2.5.3. Event asynchronous bridge
2.5.4. Channel asynchronous bridge
2.5.5. Cross Trigger to System Trace Macrocell
2.6. Trace sink components
2.6.1. Trace Port Interface Unit
2.6.2. Embedded Trace Buffer
2.7. Authentication bridges
2.7.1. Authentication replicator
2.7.2. Authentication asynchronous bridge
2.7.3. Authentication synchronous bridge
2.8. Granular Power Requester
3. Programmers Model
3.1. About the programmers model
3.2. Granular Power Requester register summary
3.3. Granular Power Requester register descriptions
3.3.1. Debug Power Request register
3.3.2. Debug Power Acknowledge register
3.3.3. Integration Mode Control register
3.3.4. Claim Tag Set register
3.3.5. Claim Tag Clear register
3.3.6. Lock Access Register
3.3.7. Lock Status Register
3.3.8. Authentication Status register
3.3.9. Device Architecture register
3.3.10. Device Configuration register
3.3.11. Device Type Identifier register
3.3.12. Peripheral ID4 Register
3.3.13. Peripheral ID0 Register
3.3.14. Peripheral ID1 Register
3.3.15. Peripheral ID2 Register
3.3.16. Peripheral ID3 Register
3.3.17. Component ID0 Register
3.3.18. Component ID1 Register
3.3.19. Component ID2 Register
3.3.20. Component ID3 Register
3.4. APB interconnect register summary
3.5. APB interconnect register descriptions
3.5.1. ROM Table Entry
3.5.2. Peripheral ID4 Register
3.5.3. Peripheral ID0 Register
3.5.4. Peripheral ID1 Register
3.5.5. Peripheral ID2 Register
3.5.6. Peripheral ID3 Register
3.5.7. Component ID0 Register
3.5.8. Component ID1 Register
3.5.9. Component ID2 Register
3.5.10. Component ID3 Register
3.6. ATB funnel register summary
3.7. ATB funnel register descriptions
3.7.1. Funnel Control register
3.7.2. Priority Control Register
3.7.3. Integration Test ATB Data0 register
3.7.4. Integration Test ATB Control 2 Register
3.7.5. Integration Test ATB Control 1 Register
3.7.6. Integration Test ATB Control 0 Register
3.7.7. Integration Mode Control register
3.7.8. Claim Tag Set register
3.7.9. Claim Tag Clear register
3.7.10. Lock Access Register
3.7.11. Lock Status Register
3.7.12. Authentication Status register
3.7.13. Device Configuration register
3.7.14. Device Type Identifier register
3.7.15. Peripheral ID4 Register
3.7.16. Peripheral ID0 Register
3.7.17. Peripheral ID1 Register
3.7.18. Peripheral ID2 Register
3.7.19. Peripheral ID3 Register
3.7.20. Component ID0 Register
3.7.21. Component ID1 Register
3.7.22. Component ID2 Register
3.7.23. Component ID3 Register
3.8. ATB replicator register summary
3.9. ATB replicator register descriptions
3.9.1. ID filtering for ATB master port 0
3.9.2. ID filtering for ATB master port 1
3.9.3. Integration Mode ATB Control 0 Register
3.9.4. Integration Mode ATB Control 1 Register
3.9.5. Integration Mode Control register
3.9.6. Claim Tag Set register
3.9.7. Claim Tag Clear register
3.9.8. Lock Access Register
3.9.9. Lock Status Register
3.9.10. Authentication Status register
3.9.11. Device Configuration register
3.9.12. Device Type Identifier register
3.9.13. Peripheral ID4 Register
3.9.14. Peripheral ID0 Register
3.9.15. Peripheral ID1 Register
3.9.16. Peripheral ID2 Register
3.9.17. Peripheral ID3 Register
3.9.18. Component ID0 Register
3.9.19. Component ID1 Register
3.9.20. Component ID2 Register
3.9.21. Component ID3 Register
3.10. ETB register summary
3.11. ETB register descriptions
3.11.1. ETB RAM Depth register
3.11.2. ETB Status register
3.11.3. ETB RAM Read Data register
3.11.4. ETB RAM Read Pointer register
3.11.5. ETB RAM Write Pointer register
3.11.6. ETB Trigger Counter register
3.11.7. ETB Control register
3.11.8. ETB RAM Write Data register
3.11.9. ETB Formatter and Flush Status Register
3.11.10. ETB Formatter and Flush Control Register
3.11.11. Integration Test Miscellaneous Output register 0
3.11.12. Integration Test Trigger In and Flush In Acknowledge register
3.11.13. Integration Test Trigger In and Flush In register
3.11.14. Integration Test ATB Data register 0
3.11.15. Integration Test ATB Control Register 2
3.11.16. Integration Test ATB Control Register 1
3.11.17. Integration Test ATB Control Register 0
3.11.18. Integration Mode Control register
3.11.19. Claim Tag Set register
3.11.20. Claim Tag Clear register
3.11.21. Lock Access Register
3.11.22. Lock Status Register
3.11.23. Authentication Status register
3.11.24. Device Configuration register
3.11.25. Device Type Identifier register
3.11.26. Peripheral ID4 Register
3.11.27. Peripheral ID0 Register
3.11.28. Peripheral ID1 Register
3.11.29. Peripheral ID2 Register
3.11.30. Peripheral ID3 Register
3.11.31. Component ID0 Register
3.11.32. Component ID1 Register
3.11.33. Component ID2 Register
3.11.34. Component ID3 Register
3.12. TPIU register summary
3.13. TPIU register descriptions
3.13.1. Supported Port Size register
3.13.2. Current Port Size register
3.13.3. Supported Trigger Modes register
3.13.4. Trigger Counter Value register
3.13.5. Trigger Multiplier register
3.13.6. Supported Test Patterns/Modes register
3.13.7. Current Test Pattern/Modes register
3.13.8. TPIU Test Pattern Repeat Counter Register
3.13.9. Formatter and Flush Status Register
3.13.10. Formatter and Flush Control Register
3.13.11. Formatter Synchronization Counter Register
3.13.12. TPIU EXCTL In Port register
3.13.13. TPIU EXCTL Out Port register
3.13.14. Integration Test Trigger In and Flush In Acknowledge register
3.13.15. Integration Test Trigger In and Flush In register
3.13.16. Integration Test ATB Data register 0
3.13.17. Integration Test ATB Control Register 2
3.13.18. Integration Test ATB Control Register 1
3.13.19. Integration Test ATB Control Register 0
3.13.20. Integration Mode Control register
3.13.21. Claim Tag Set register
3.13.22. Claim Tag Clear register
3.13.23. Lock Access Register
3.13.24. Lock Status Register
3.13.25. Authentication Status register
3.13.26. Device Configuration register
3.13.27. Device Type Identifier register
3.13.28. Peripheral ID4 Register
3.13.29. Peripheral ID0 Register
3.13.30. Peripheral ID1 Register
3.13.31. Peripheral ID2 Register
3.13.32. Peripheral ID3 Register
3.13.33. Component ID0 Register
3.13.34. Component ID1 Register
3.13.35. Component ID2 Register
3.13.36. Component ID3 Register
3.14. CTI register summary
3.15. CTI register descriptions
3.15.1. CTI Control register
3.15.2. CTI Interrupt Acknowledge register
3.15.3. CTI Application Trigger Set register
3.15.4. CTI Application Trigger Clear register
3.15.5. CTI Application Pulse register
3.15.6. CTI Trigger 0 to Channel Enable register
3.15.7. CTI Trigger 1 to Channel Enable register
3.15.8. CTI Trigger 2 to Channel Enable register
3.15.9. CTI Trigger 3 to Channel Enable register
3.15.10. CTI Trigger 4 to Channel Enable register
3.15.11. CTI Trigger 5 to Channel Enable register
3.15.12. CTI Trigger 6 to Channel Enable register
3.15.13. CTI Trigger 7 to Channel Enable register
3.15.14. CTI Channel to Trigger 0 Enable register
3.15.15. CTI Channel to Trigger 1 Enable register
3.15.16. CTI Channel to Trigger 2 Enable register
3.15.17. CTI Channel to Trigger 3 Enable register
3.15.18. CTI Channel to Trigger 4 Enable register
3.15.19. CTI Channel to Trigger 5 Enable register
3.15.20. CTI Channel to Trigger 6 Enable register
3.15.21. CTI Channel to Trigger 7 Enable register
3.15.22. CTI Trigger In Status register
3.15.23. CTI Trigger Out Status register
3.15.24. CTI Channel In Status register
3.15.25. CTI Channel Out Status register
3.15.26. Enable CTI Channel Gate register
3.15.27. External Multiplexer Control register
3.15.28. Integration Test Channel Input Acknowledge register
3.15.29. Integration Test Trigger Input Acknowledge register
3.15.30. Integration Test Channel Output register
3.15.31. Integration Test Trigger Output register
3.15.32. Integration Test Channel Output Acknowledge register
3.15.33. Integration Test Trigger Output Acknowledge register
3.15.34. Integration Test Channel Input register
3.15.35. Integration Test Trigger Input register
3.15.36. Integration Mode Control register
3.15.37. Claim Tag Set register
3.15.38. Claim Tag Clear register
3.15.39. Lock Access Register
3.15.40. Lock Status Register
3.15.41. Authentication Status register
3.15.42. Device Configuration register
3.15.43. Device Type Identifier register
3.15.44. Peripheral ID4 Register
3.15.45. Peripheral ID0 Register
3.15.46. Peripheral ID1 Register
3.15.47. Peripheral ID2 Register
3.15.48. Peripheral ID3 Register
3.15.49. Component ID0 Register
3.15.50. Component ID1 Register
3.15.51. Component ID2 Register
3.15.52. Component ID3 Register
3.16. DAP register summary
3.16.1. JTAG-AP register summary
3.16.2. AHB-AP register summary
3.16.3. AXI-AP register summary
3.16.4. APB-AP register summary
3.16.5. Debug port register summary
3.17. DAP register descriptions
3.17.1. JTAG-AP register descriptions
3.17.2. AHB-AP register descriptions
3.17.3. AXI-AP registers descriptions
3.17.4. APB-AP registers description
3.17.5. Debug port implementation-specific registers
3.18. Timestamp generator register summary
3.19. Timestamp generator registers description
3.19.1. Counter Control Register, CNTCR
3.19.2. Counter Status Register, CNTSR
3.19.3. Current Counter Value Lower register, CNTCVL
3.19.4. Current Counter Value Upper register, CNTCVU
3.19.5. Base Frequency ID register, CNTFID0
3.19.6. Peripheral ID4 Register, PIDR4
3.19.7. Peripheral ID0 Register, PIDR0
3.19.8. Peripheral ID1 Register, PIDR1
3.19.9. Peripheral ID2 Register, PIDR2
3.19.10. Peripheral ID3 Register, PIDR3
3.19.11. Component ID0 Register, CIDR0
3.19.12. Component ID1 Register, CIDR1
3.19.13. Component ID2 Register, CIDR2
3.19.14. Component ID3 Register, CIDR3
4. Debug Access Port
4.1. About the Debug Access Port
4.1.1. DAP flow of control
4.2. SWJ-DP
4.2.1. Structure of the SWJ-DP
4.2.2. Operation of the SWJ-DP
4.2.3. JTAG and SWD interface
4.2.4. Operation in JTAG-DP mode
4.2.5. Operation in SW-DP mode
4.2.6. Clock, reset, and power domain support
4.2.7. SWD and JTAG selection mechanism
4.2.8. Common debug port features and registers
4.3. DAPBUS interconnect
4.3.1. Clock and reset
4.3.2. Functional interfaces
4.3.3. Operation
4.4. DAPBUS asynchronous bridge
4.4.1. Clock and reset
4.4.2. Functional interfaces
4.4.3. Functional description
4.4.4. Low-power features
4.5. DAPBUS synchronous bridge
4.5.1. Clock and reset
4.5.2. Functional interface
4.5.3. Functional description
4.5.4. Low power features
4.6. JTAG-AP
4.6.1. External interfaces
4.6.2. RTCK connections
4.7. AXI-AP
4.7.1. Clock and reset
4.7.2. Functional interfaces
4.7.3. AXI-AP features
4.7.4. DAP transfer abort
4.7.5. Error responses
4.7.6. AXI transfers
4.7.7. Packed transfers
4.7.8. Valid combinations of AxCACHE and AxDOMAIN
4.8. AHB-AP
4.8.1. Clock and reset
4.8.2. External interfaces
4.8.3. Implementation features
4.8.4. DAP transfers
4.8.5. Differentiation between system and access port initiated error responses
4.9. APB-AP
4.9.1. Clock and reset
4.9.2. External interfaces
4.9.3. Implementation features
4.9.4. DAP transfers
4.9.5. Authentication requirements for APB-AP
5. APB Interconnect Components
5.1. APB Interconnect with ROM table
5.1.1. Clock and reset
5.1.2. Functional interfaces
5.1.3. Device operation
5.2. APB asynchronous bridge
5.2.1. Clock and reset
5.2.2. Functional interfaces
5.2.3. Low-power features
5.3. APB synchronous bridge
5.3.1. Clock and reset
5.3.2. Functional interface
5.3.3. Functional description
5.3.4. Low-power features
6. ATB Interconnect Components
6.1. ATB replicator
6.1.1. Clock and reset
6.1.2. Functional interfaces
6.1.3. Functional overview
6.2. ATB funnel
6.2.1. Clock and reset
6.2.2. Functional interface
6.2.3. ATB slave interface enable
6.2.4. Arbitration
6.2.5. Cascaded funnel support
6.2.6. Topology detection
6.2.7. Non-programmable funnel
6.3. ATB upsizer
6.3.1. Clocks and reset
6.3.2. Functional interface
6.3.3. Component functionality
6.4. ATB downsizer
6.4.1. Clocks and reset
6.4.2. Functional interface
6.4.3. Component functionality
6.5. ATB asynchronous bridge
6.5.1. Functional interfaces
6.5.2. Clocks and resets
6.5.3. Device operation
6.5.4. Low-power features
6.6. ATB synchronous bridge
6.6.1. Clock and reset
6.6.2. Functional interfaces
6.6.3. Operation
6.6.4. Low-power control
7. Timestamp Components
7.1. About the timestamp components
7.2. Timestamp generator
7.2.1. Clock and reset
7.2.2. Processor generic time
7.2.3. Control APB interface
7.2.4. Read-only APB interface
7.2.5. hltdbg signal
7.2.6. Counter overflow
7.3. Timestamp encoder
7.3.1. Clock and reset
7.4. Narrow timestamp replicator
7.4.1. Clock and reset
7.5. Narrow timestamp asynchronous bridge
7.5.1. Functional interfaces
7.5.2. Clocks and resets
7.5.3. Operation
7.5.4. Low-power features
7.5.5. Timestamp recovery from stopped clock
7.6. Narrow timestamp synchronous bridge
7.6.1. Functional interfaces
7.6.2. Clocks and resets
7.6.3. Functionality
7.6.4. Low-power features
7.7. Timestamp decoder
7.7.1. Clock and reset
7.8. Timestamp interpolator
7.8.1. Clock and reset
7.8.2. Functional interface
7.8.3. Limitations
8. Embedded Cross Trigger
8.1. Cross-triggering components
8.1.1. Event signaling protocol
8.2. CTI
8.2.1. Clocks and resets
8.2.2. Functional interface
8.2.3. Disabling a CTI
8.2.4. Authentication
8.3. CTM
8.3.1. Clocks and resets
8.3.2. Functional interface
8.4. Event asynchronous bridge
8.4.1. Clocks and resets
8.4.2. Connecting eventack signals
8.5. Register slice
8.6. Channel asynchronous bridge
8.7. Cross Trigger to System Trace Macrocell
9. Trace Port Interface Unit
9.1. About the Trace Port Interface Unit
9.2. Clocks and resets
9.3. Functional interfaces
9.4. Trace out port
9.4.1. Signals of the trace out port
9.4.2. traceclk alignment
9.4.3. tracectl removal
9.4.4. tracectl encoding
9.4.5. Off-chip based traceclkin
9.5. Trace port triggers
9.5.1. Correlation with afvalid
9.6. Programming the TPIU for trace capture
9.7. Example configuration scenarios
9.7.1. Capturing trace after an event and stopping
9.7.2. Only indicating triggers and continuing to flush
9.7.3. Multiple trigger indications
9.7.4. Independent triggering and flushing
9.8. TPIU pattern generator
9.8.1. Pattern generator modes of operation
9.8.2. Supported options
10. Embedded Trace Buffer
10.1. About the ETB
10.2. Clocks and resets
10.3. Functional Interfaces
10.3.1. Cross-triggering events
10.3.2. Memory BIST interface
10.4. ETB trace capture and formatting
10.4.1. Modes of operation
10.4.2. Stopping trace
10.4.3. Flush assertion
10.4.4. Triggers
10.5. ETB RAM support
10.5.1. Access sizes
10.5.2. BIST interface
10.5.3. RAM instantiation
11. Granular Power Requester
11.1. Granular Power Requester interfaces
11.1.1. Clock and reset
11.1.2. Functional interfaces
11.1.3. Device unlocking
A. Signal Descriptions
A.1. Debug Access Port signals
A.1.1. Serial wire or JTAG Debug Port signals
A.1.2. DAPBUS interconnect signals
A.1.3. DAPBUS asynchronous bridge signals
A.1.4. DAPBUS synchronous bridge signals
A.1.5. JTAG - Access Port signals
A.1.6. AXI - Access Port signals
A.1.7. AHB - Access Port signals
A.1.8. APB - Access Port signals
A.2. APB component signals
A.2.1. APB interconnect signals
A.2.2. APB asynchronous bridge signals
A.2.3. APB synchronous bridge signals
A.3. ATB interconnect signals
A.3.1. ATB replicator signals
A.3.2. ATB trace funnel signals
A.3.3. ATB upsizer signals
A.3.4. ATB downsizer signals
A.3.5. ATB asynchronous bridge signals
A.3.6. ATB synchronous bridge signals
A.4. Timestamp component signals
A.4.1. Timestamp generator signals
A.4.2. Timestamp encoder signals
A.4.3. Narrow timestamp replicator signals
A.4.4. Narrow timestamp asynchronous bridge signals
A.4.5. Narrow timestamp synchronous bridge signals
A.4.6. Timestamp decoder signals
A.4.7. Timestamp interpolator signals
A.5. Trigger component signals
A.5.1. Cross Trigger Interface signals
A.5.2. Cross Trigger Matrix signals
A.5.3. Event asynchronous bridge signals
A.6. Trace sink signals
A.6.1. Trace Port Interface Unit signals
A.6.2. Embedded Trace Buffer signals
A.7. Authentication and event bridges
A.7.1. Authentication asynchronous bridge signals
A.7.2. Authentication synchronous bridge signals
A.7.3. Authentication replicator
A.8. Granular power requester signals
B. Revisions

List of Figures

1. Key to timing diagram conventions
1.1. CoreSight SoC-400 system
1.2. Design and validation workflow with CoreSight SoC-400
2.1. SWJ-DP block diagram
2.2. DAPBUS interconnect block diagram
2.3. DAPBUS asynchronous bridge block diagram
2.4. DAPBUS synchronous bridge block diagram
2.5. JTAG Access Port block diagram
2.6. AXI Access Port block diagram
2.7. AHB Access Port block diagram
2.8. APB Access Port block diagram
2.9. APB interconnect with ROM table block diagram
2.10. APB asynchronous bridge block diagram
2.11. APB synchronous bridge block diagram
2.12. ATB replicator block diagram
2.13. ATB funnel block diagram
2.14. ATB upsizer block diagram
2.15. ATB downsizer block diagram
2.16. ATB asynchronous bridge block diagram
2.17. ATB synchronous bridge block diagram
2.18. Timestamp generator block diagram
2.19. Timestamp encoder block diagram
2.20. Narrow timestamp replicator block diagram
2.21. Narrow timestamp asynchronous bridge block diagram
2.22. Narrow timestamp synchronous bridge block diagram
2.23. Timestamp decoder block diagram
2.24. Timestamp interpolator block diagram
2.25. Cross Trigger Interface block diagram
2.26. Cross Trigger Matrix block diagram
2.27. Event asynchronous bridge block diagram
2.28. cxctitocxstm component
2.29. Trace Port Interface Unit block diagram
2.30. Embedded Trace Buffer block diagram
2.31. Authentication replicator block diagram
2.32. Authentication asynchronous bridge block diagram
2.33. Authentication synchronous bridge block diagram
2.34. Granular Power Requester block diagram
3.1. ITCTRL register bit assignments
3.2. CLAIMSET register bit assignments
3.3. CLAIMCLR register bit assignments
3.4. LAR bit assignments
3.5. LSR bit assignments
3.6. AUTHSTATUS register bit assignments
3.7. DEVARCH register bit assignments
3.8. DEVID register bit assignments
3.9. DEVTYPE register bit assignments
3.10. PIDR4 bit assignments
3.11. PIDR0 bit assignments
3.12. PIDR1 bit assignments
3.13. PIDR2 bit assignments
3.14. PIDR3 bit assignments
3.15. CIDR0 bit assignments
3.16. CIDR1 bit assignments
3.17. CIDR2 bit assignments
3.18. CIDR3 bit assignments
3.19. ROM_ENTRY_n register bit assignments
3.20. PIDR4 bit assignments
3.21. PIDR0 bit assignments
3.22. PIDR1 bit assignments
3.23. PIDR2 bit assignments
3.24. PIDR3 bit assignments
3.25. CIDR0 bit assignments
3.26. CIDR1 bit assignments
3.27. CIDR2 bit assignments
3.28. CIDR3 bit assignments
3.29. Ctrl_Reg bit assignments
3.30. Priority_Ctrl_Reg bit assignments
3.31. ITATBDATA0 register bit assignments
3.32. ITATBCTR2 bit assignments
3.33. ITATBCTR1 bit assignments
3.34. ITATBCTR0 bit assignments
3.35. ITCTRL register bit assignments
3.36. CLAIMSET register bit assignments
3.37. CLAIMCLR register bit assignments
3.38. LAR bit assignments
3.39. LSR bit assignments
3.40. AUTHSTATUS register bit assignments
3.41. DEVID register bit assignments
3.42. DEVTYPE register bit assignments
3.43. PIDR4 bit assignments
3.44. PIDR0 bit assignments
3.45. PIDR1 bit assignments
3.46. PIDR2 bit assignments
3.47. PIDR3 bit assignments
3.48. CIDR0 bit assignments
3.49. CIDR1 bit assignments
3.50. CIDR2 bit assignments
3.51. CIDR3 bit assignments
3.52. IDFILTER0 register bit assignments
3.53. IDFILTER1 register bit assignments
3.54. ITATBCTR0 bit assignments
3.55. ITATBCTR1 bit assignments
3.56. ITCTRL register bit assignments
3.57. CLAIMSET register bit assignments
3.58. CLAIMCLR register bit assignments
3.59. LAR bit assignments
3.60. LSR bit assignments
3.61. AUTHSTATUS register bit assignments
3.62. DEVID register bit assignments
3.63. DEVTYPE register bit assignments
3.64. PIDR4 bit assignments
3.65. PIDR0 bit assignments
3.66. PIDR1 bit assignments
3.67. PIDR2 bit assignments
3.68. PIDR3 bit assignments
3.69. CIDR0 bit assignments
3.70. CIDR1 bit assignments
3.71. CIDR2 bit assignments
3.72. CIDR3 bit assignments
3.73. RDP register bit assignments
3.74. STS register bit assignments
3.75. RRD register bit assignments
3.76. RRP register bit assignments
3.77. RWP register bit assignments
3.78. TRG register bit assignments
3.79. CTL register bit assignments
3.80. RWD register bit assignments
3.81. FFSR bit assignments
3.82. FFCR bit assignments
3.83. ITMISCOP0 register bit assignments
3.84. ITTRFLINACK register bit assignments
3.85. ITTRFLIN register bit assignments
3.86. ITATBDATA0 register bit assignments
3.87. ITATBCTR2 bit assignments
3.88. ITATBCTR1 bit assignments
3.89. ITATBCTR0 bit assignments
3.90. ITCTRL register bit assignments
3.91. CLAIMSET register bit assignments
3.92. CLAIMCLR register bit assignments
3.93. LAR bit assignments
3.94. LSR bit assignments
3.95. AUTHSTATUS register bit assignments
3.96. DEVID register bit assignments
3.97. DEVTYPE register bit assignments
3.98. PIDR4 bit assignments
3.99. PIDR0 bit assignments
3.100. PIDR1 bit assignments
3.101. PIDR2 bit assignments
3.102. PIDR3 bit assignments
3.103. CIDR0 bit assignments
3.104. CIDR1 bit assignments
3.105. CIDR2 bit assignments
3.106. CIDR3 bit assignments
3.107. Supported_Port_Sizes register bit assignments
3.108. Current_port_size register bit assignments
3.109. Supported_trigger_modes register bit assignments
3.110. Trigger_counter_value register bit assignments
3.111. Trigger_multiplier register bit assignments
3.112. Supported_test_pattern_modes register bit assignments
3.113. Current_test_pattern_mode register bit assignments
3.114. TPRCR bit assignments
3.115. FFSR bit assignments
3.116. FFCR bit assignments
3.117. FSCR bit assignments
3.118. EXTCTL_In_Port register bit assignments
3.119. EXTCTL_Out_Port register bit assignments
3.120. ITTRFLINACK register bit assignments
3.121. ITTRFLIN register bit assignments
3.122. ITATBDATA0 register bit assignments
3.123. ITATBCTR2 bit assignments
3.124. ITATBCTR1 bit assignments
3.125. ITATBCTR0 bit assignments
3.126. ITCTRL register bit assignments
3.127. CLAIMSET register bit assignments
3.128. CLAIMCLR register bit assignments
3.129. LAR bit assignments
3.130. LSR bit assignments
3.131. AUTHSTATUS register bit assignments
3.132. DEVID register bit assignments
3.133. DEVTYPE register bit assignments
3.134. PIDR4 bit assignments
3.135. PIDR0 bit assignments
3.136. PIDR1 bit assignments
3.137. PIDR2 bit assignments
3.138. PIDR3 bit assignments
3.139. CIDR0 bit assignments
3.140. CIDR1 bit assignments
3.141. CIDR2 bit assignments
3.142. CIDR3 bit assignments
3.143. CTICONTROL register bit assignments
3.144. CTIINTACK register bit assignments
3.145. CTIAPPSET register bit assignments
3.146. CTIAPPCLEAR register bit assignments
3.147. CTIAPPPULSE register bit assignments
3.148. CTIINEN0 register bit assignments
3.149. CTIINEN1 register bit assignments
3.150. CTIINEN2 register bit assignments
3.151. CTIINEN3 register bit assignments
3.152. CTIINEN4 register bit assignments
3.153. CTIINEN5 register bit assignments
3.154. CTIINEN6 register bit assignments
3.155. CTIINEN7 register bit assignments
3.156. CTIOUTEN0 register bit assignments
3.157. CTIOUTEN1 register bit assignments
3.158. CTIOUTEN2 register bit assignments
3.159. CTIOUTEN3 register bit assignments
3.160. CTIOUTEN4 register bit assignments
3.161. CTIOUTEN5 register bit assignments
3.162. CTIOUTEN6 register bit assignments
3.163. CTIOUTEN7 register bit assignments
3.164. CTITRIGINSTATUS register bit assignments
3.165. CTITRIGOUTSTATUS register bit assignments
3.166. CTICHINSTATUS register bit assignments
3.167. CTICHOUTSTATUS register bit assignments
3.168. CTIGATE register bit assignments
3.169. ASICCTL register bit assignments
3.170. ITCHINACK register bit assignments
3.171. ITTRIGINACK register bit assignments
3.172. ITCHOUT register bit assignments
3.173. ITTRIGOUT register bit assignments
3.174. ITCHOUTACK register bit assignments
3.175. ITTRIGOUTACK register bit assignments
3.176. ITCHIN register bit assignments
3.177. ITTRIGIN register bit assignments
3.178. ITCTRL register bit assignments
3.179. CLAIMSET register bit assignments
3.180. CLAIMCLR register bit assignments
3.181. LAR bit assignments
3.182. LSR bit assignments
3.183. AUTHSTATUS register bit assignments
3.184. DEVID register bit assignments
3.185. DEVTYPE register bit assignments
3.186. PIDR4 bit assignments
3.187. PIDR0 bit assignments
3.188. PIDR1 bit assignments
3.189. PIDR2 bit assignments
3.190. PIDR3 bit assignments
3.191. CIDR0 bit assignments
3.192. CIDR1 bit assignments
3.193. CIDR2 bit assignments
3.194. CIDR3 bit assignments
3.195. JTAG-AP CSW register bit assignments
3.196. JTAG-AP Port Select register bit assignments
3.197. JTAG-AP Port Status register bit assignments
3.198. JTAG-AP Identification Register bit assignments
3.199. AHB-AP CSW register bit assignments
3.200. AHB-AP Identification Register bit assignments
3.201. AXI-AP CSW register bit assignments
3.202. AXI-AP Transfer Address register bit assignments
3.203. AXI-AP Data RW register bit assignments
3.204. AXI-AP Banked DATA register bit assignments
3.205. ACE Barrier Transaction register bit assignments
3.206. AXI-AP Debug Base Address register, BASE[63:32] bit assignments
3.207. AXI-AP Debug Base Address register, BASE[31:0] bit assignments
3.208. AXI-AP Configuration register bit assignments
3.209. AXI-AP Identification Register bit assignments
3.210. APB-AP Control/Status Word register bit assignments
3.211. APB-AP Transfer Address register bit assignments
3.212. APB-AP Identification register bit assignments
3.213. JTAG-DP ABORT bit assignments
3.214. SW-DP ABORT bit assignments
3.215. Identification Code register bit assignments
3.216. Debug Port Identification register bit assignments
3.217. Control/Status Register bit assignments
3.218. AP Select Register bit assignments
3.219. Data Link Control Register bit assignments
3.220. Target Identification register bit assignments
3.221. Data Link Protocol Identification Register bit assignments
3.222. CNTCR bit assignments
3.223. CNTSR bit assignments
3.224. CNTCVL register bit assignments
3.225. CNTCUV register bit assignments
3.226. CNTFID0 register bit assignments
3.227. PIDR4 bit assignments
3.228. PIDR0 bit assignments
3.229. PIDR1 bit assignments
3.230. PIDR2 bit assignments
3.231. PIDR3 bit assignments
3.232. CIDR0 bit assignments
3.233. CIDR1 bit assignments
3.234. CIDR2 bit assignments
3.235. CIDR3 bit assignments
4.1. Structure of the CoreSight SoC-400 DAP components
4.2. DAP flow of control
4.3. SWJ-DP
4.4. SW-DP to DAP bus timing for write
4.5. SW-DP to DAP bus timing for read
4.6. SW-DP idle timing
6.1. ATB funnel minimum hold time example
7.1. Timestamp example system
9.1. Externally derived traceclk
9.2. Capturing trace after an event and stopping
9.3. Multiple trigger indications from flushes
9.4. Independent triggering during repeated flushes
10.1. Conditions for stopping trace capture
10.2. Generation of flush on flushin
10.3. Generation of flush from a trigger event
10.4. Generation of a flush on manual
10.5. Generation of a trigger request with continuos formatting enabled

List of Tables

1. Typographical conventions
1.1. CoreSight SoC-400 block summary
3.1. cxgpr register summary
3.2. CPWRUPREQ register bit assignments
3.3. CPWRUPACK register bit assignments
3.4. ITCTRL register bit assignments
3.5. CLAIMSET register bit assignments
3.6. CLAIMCLR register bit assignments
3.7. LAR bit assignments
3.8. LSR bit assignments
3.9. AUTHSTATUS register bit assignments
3.10. DEVARCH register bit assignments
3.11. DEVID register bit assignments
3.12. DEVTYPE register bit assignments
3.13. PIDR4 bit assignments
3.14. PIDR0 bit assignments
3.15. PIDR1 bit assignments
3.16. PIDR2 bit assignments
3.17. PIDR3 bit assignments
3.18. CIDR0 bit assignments
3.19. CIDR1 bit assignments
3.20. CIDR2 bit assignments
3.21. CIDR3 bit assignments
3.22. APB interconnect register summary
3.23. ROM_ENTRY_n register bit assignments
3.24. PIDR4 bit assignments
3.25. PIDR0 bit assignments
3.26. PIDR1 bit assignments
3.27. PIDR2 bit assignments
3.28. PIDR3 bit assignments
3.29. CIDR0 bit assignments
3.30. CIDR1 bit assignments
3.31. CIDR2 bit assignments
3.32. CIDR3 bit assignments
3.33. ATB funnel register summary
3.34. Ctrl_Reg bit assignments
3.35. Priority_Ctrl_Reg bit assignments
3.36. ITATBDATA0 register bit assignments
3.37. ITATBCTR2 bit assignments
3.38. ITATBCTR1 bit assignments
3.39. ITATBCTR0 bit assignments
3.40. ITCTRL register bit assignments
3.41. CLAIMSET register bit assignments
3.42. CLAIMCLR register bit assignments
3.43. LAR bit assignments
3.44. LSR bit assignments
3.45. AUTHSTATUS register bit assignments
3.46. DEVID register bit assignments
3.47. DEVTYPE register bit assignments
3.48. PIDR4 bit assignments
3.49. PIDR0 bit assignments
3.50. PIDR1 bit assignments
3.51. PIDR2 bit assignments
3.52. PIDR3 bit assignments
3.53. CIDR0 bit assignments
3.54. CIDR1 bit assignments
3.55. CIDR2 bit assignments
3.56. CIDR3 bit assignments
3.57. ATB replicator register summary
3.58. IDFILTER0 register bit assignments
3.59. IDFILTER1 register bit assignments
3.60. ITATBCTR0 bit assignments
3.61. ITATBCTR1 bit assignments
3.62. ITCTRL register bit assignments
3.63. CLAIMSET register bit assignments
3.64. CLAIMCLR register bit assignments
3.65. LAR bit assignments
3.66. LSR bit assignments
3.67. AUTHSTATUS register bit assignments
3.68. DEVID register bit assignments
3.69. DEVTYPE register bit assignments
3.70. PIDR4 bit assignments
3.71. PIDR0 bit assignments
3.72. PIDR1 bit assignments
3.73. PIDR2 bit assignments
3.74. PIDR3 bit assignments
3.75. CIDR0 bit assignments
3.76. CIDR1 bit assignments
3.77. CIDR2 bit assignments
3.78. CIDR3 bit assignments
3.79. ETB register summary
3.80. RDP register bit assignments
3.81. STS register bit assignments
3.82. RRD register bit assignments
3.83. RRP register bit assignments
3.84. RWP register bit assignments
3.85. TRG register bit assignments
3.86. CTL register bit assignments
3.87. RWD register bit assignments
3.88. FFSR bit assignments
3.89. FFCR bit assignments
3.90. ITMISCOP0 register bit assignments
3.91. ITTRFLINACK register bit assignments
3.92. ITTRFLIN register bit assignments
3.93. ITATBDATA0 register bit assignments
3.94. ITATBCTR2 bit assignments
3.95. ITATBCTR1 bit assignments
3.96. ITATBCTR0 bit assignments
3.97. ITCTRL register bit assignments
3.98. CLAIMSET register bit assignments
3.99. CLAIMCLR register bit assignments
3.100. LAR bit assignments
3.101. LSR bit assignments
3.102. AUTHSTATUS register bit assignments
3.103. DEVID register bit assignments
3.104. DEVTYPE register bit assignments
3.105. PIDR4 bit assignments
3.106. PIDR0 bit assignments
3.107. PIDR1 bit assignments
3.108. PIDR2 bit assignments
3.109. PIDR3 bit assignments
3.110. CIDR0 bit assignments
3.111. CIDR1 bit assignments
3.112. CIDR2 bit assignments
3.113. CIDR3 bit assignments
3.114. TPIU register summary
3.115. Supported_Port_Sizes register bit assignments
3.116. Current_port_size register bit assignments
3.117. Supported_trigger_modes register bit assignments
3.118. Trigger_counter_value register bit assignments
3.119. Trigger_multiplier register bit assignments
3.120. Supported_test_pattern_modes register bit assignments
3.121. Current_test_pattern_mode register bit assignments
3.122. TPRCR bit assignments
3.123. FFSR bit assignments
3.124. FFCR bit assignments
3.125. FSCR bit assignments
3.126. EXTCTL_In_Port register bit assignments
3.127. EXTCTL_Out_Port register bit assignments
3.128. ITTRFLINACK register bit assignments
3.129. ITTRFLIN register bit assignments
3.130. ITATBDATA0 register bit assignments
3.131. ITATBCTR2 bit assignments
3.132. ITATBCTR1 bit assignments
3.133. ITATBCTR0 bit assignments
3.134. ITCTRL register bit assignments
3.135. CLAIMSET register bit assignments
3.136. CLAIMCLR register bit assignments
3.137. LAR bit assignments
3.138. LSR bit assignments
3.139. AUTHSTATUS register bit assignments
3.140. DEVID register bit assignments
3.141. DEVTYPE register bit assignments
3.142. PIDR4 bit assignments
3.143. PIDR0 bit assignments
3.144. PIDR1 bit assignments
3.145. PIDR2 bit assignments
3.146. PIDR3 bit assignments
3.147. CIDR0 bit assignments
3.148. CIDR1 bit assignments
3.149. CIDR2 bit assignments
3.150. CIDR3 bit assignments
3.151. CTI register summary
3.152. CTICONTROL register bit assignments
3.153. CTIINTACK register bit assignments
3.154. CTIAPPSET register bit assignments
3.155. CTIAPPCLEAR register bit assignments
3.156. CTIAPPPULSE register bit assignments
3.157. CTIINEN0 register bit assignments
3.158. CTIINEN1 register bit assignments
3.159. CTIINEN2 register bit assignments
3.160. CTIINEN3 register bit assignments
3.161. CTIINEN4 register bit assignments
3.162. CTIINEN5 register bit assignments
3.163. CTIINEN6 register bit assignments
3.164. CTIINEN7 register bit assignments
3.165. CTIOUTEN0 register bit assignments
3.166. CTIOUTEN1 register bit assignments
3.167. CTIOUTEN2 register bit assignments
3.168. CTIOUTEN3 register bit assignments
3.169. CTIOUTEN4 register bit assignments
3.170. CTIOUTEN5 register bit assignments
3.171. CTIOUTEN6 register bit assignments
3.172. CTIOUTEN7 register bit assignments
3.173. CTITRIGINSTATUS register bit assignments
3.174. CTITRIGOUTSTATUS register bit assignments
3.175. CTICHINSTATUS register bit assignments
3.176. CTICHOUTSTATUS register bit assignments
3.177. CTIGATE register bit assignments
3.178. ASICCTL register bit assignments
3.179. ITCHINACK register bit assignments
3.180. ITTRIGINACK register bit assignments
3.181. ITCHOUT register bit assignments
3.182. ITTRIGOUT register bit assignments
3.183. ITCHOUTACK register bit assignments
3.184. ITTRIGOUTACK register bit assignments
3.185. ITCHIN register bit assignments
3.186. ITTRIGIN register bit assignments
3.187. ITCTRL register bit assignments
3.188. CLAIMSET register bit assignments
3.189. CLAIMCLR register bit assignments
3.190. LAR bit assignments
3.191. LSR bit assignments
3.192. AUTHSTATUS register bit assignments
3.193. DEVID register bit assignments
3.194. DEVTYPE register bit assignments
3.195. PIDR4 bit assignments
3.196. PIDR0 bit assignments
3.197. PIDR1 bit assignments
3.198. PIDR2 bit assignments
3.199. PIDR3 bit assignments
3.200. CIDR0 bit assignments
3.201. CIDR1 bit assignments
3.202. CIDR2 bit assignments
3.203. CIDR3 bit assignments
3.204. JTAG-AP register summary
3.205. AHB-AP register summary
3.206. AXI-AP register summary
3.207. APB-AP register summary
3.208. Debug port register summary
3.209. JTAG-DP register summary
3.210. JTAG-AP CSW register bit assignments
3.211. JTAG-AP Port Select register bit assignments
3.212. JTAG-AP Port Status register bit assignments
3.213. JTAG-AP Identification Register bit assignments
3.214. AHB-AP Control/Status Word register bit assignments
3.215. AHB-AP Transfer Address register bit assignments
3.216. AHB-AP Data Read/Write register bit assignments
3.217. Banked Data register bit assignments
3.218. AHB-AP Debug Base Address register bit assignments
3.219. AHB-AP Identification Register bit assignments
3.220. AXI-AP CSW register bit assignments
3.221. AXI-AP Transfer Address register bit assignments
3.222. AXI-AP Data RW register bit assignments
3.223. AXI-AP Banked Data registers bit assignments
3.224. ACE Barrier Transaction register bit assignments
3.225. AXI-AP Debug Base Address register, BASE[63:32] bit assignments
3.226. AXI-AP Debug Base Address register, BASE[31:0] bit assignments
3.227. AXI-AP Configuration register bit assignments
3.228. AXI-AP Identification Register bit assignments
3.229. APB Control/Status Word register bit assignments
3.230. APB-AP Transfer Address register bit assignments
3.231. ABP-AP Data Read/Write register bit assignments
3.232. APB-AP Banked Data registers bit assignments
3.233. Debug Base Address register bit assignments
3.234. APB-AP Identification register bit assignments
3.235. ABORT register bit assignments
3.236. Identification Code register bit assignments
3.237. JEDEC JEP-106 manufacturer ID code, with ARM values
3.238. Debug Port Identification register bit assignments
3.239. Control/Status Register bit assignments
3.240. AP Select Register bit assignments
3.241. Data Link Control Register bit assignments
3.242. Turnaround tristate period field bit definitions
3.243. Wire operating mode bit definitions
3.244. Target Identification register bit assignments
3.245. Data Link Protocol Identification Register bit assignments
3.246. Timestamp generator register summary
3.247. CNTCR bit assignments
3.248. CNTSR bit assignments
3.249. CNTCVL register bit assignments
3.250. CNTCUV register bit assignments
3.251. CNTFID0 register bit assignments
3.252. PIDR4 bit assignments
3.253. PIDR0 bit assignments
3.254. PIDR1 bit assignments
3.255. PIDR2 bit assignments
3.256. PIDR3 bit assignments
3.257. CIDR0 bit assignments
3.258. CIDR1 bit assignments
3.259. CIDR2 bit assignments
3.260. CIDR3 bit assignments
4.1. JTAG-DP physical interface
4.2. Terms used in SW-DP timing
4.3. TARGETID input connections
4.4. JTAG to slave device signals
4.5. AXI-AP features
4.6. Difference between AXI and AP initiated error response
4.7. Valid combination of AxCACHE and AxDOMAIN values
4.8. Other AHB-AP ports
4.9. Example generation of byte lane strobes
4.10. Error responses with DAPSLVERR HIGH and TrInProg LOW
4.11. APB-AP other ports
5.1. Address bus on the master interfaces
6.1. Event sequence
9.1. Trace out port signals
9.2. Configuration tie-off signals
9.3. CoreSight representation of triggers
10.1. Cross-triggering events
10.2. ETB Memory BIST interface ports
A.1. Serial wire and JTAG debug port signals
A.2. DAPBUS interconnect signals
A.3. DAPBUS asynchronous bridge signals
A.4. DAPBUS asynchronous bridge cross-domain connections
A.5. DAPBUS synchronous bridge signals
A.6. DAP JTAG access port signals
A.7. DAP AXI access port signals
A.8. DAP AHB access port signals
A.9. DAP APB-AP signals
A.10. APB interconnect signals
A.11. APB asynchronous bridge signals
A.12. APB asynchronous bridge cross-domain connections
A.13. APB synchronous bridge signals
A.14. ATB replicator signals
A.15. ATB trace funnel signals
A.16. ATB upsizer signals
A.17. ATB downsizer signals
A.18. ATB asynchronous bridge signals
A.19. ATB asynchronous bridge cross-domain connections
A.20. ATB synchronous bridge signals
A.21. Timestamp generator signals
A.22. Timestamp encoder signals
A.23. Narrow timestamp replicator signals
A.24. Narrow timestamp asynchronous bridge signals
A.25. Narrow timestamp asynchronous bridge cross-domain connections
A.26. Narrow timestamp synchronous bridge signals
A.27. Timestamp decoder signals
A.28. Timestamp interpolator signals
A.29. CTI signals
A.30. CTM signals
A.31. Event asynchronous bridge signals
A.32. TPIU signals
A.33. ETB signals
A.34. Authentication asynchronous bridge signals
A.35. Authentication asynchronous bridge cross-domain connections
A.36. Authentication synchronous bridge signals
A.37. Authentication replicator signals
A.38. Granular power requester signals
B.1. Issue A
B.2. Differences between Issue A and Issue B
B.3. Differences between Issue B and Issue C
B.4. Differences between Issue C and Issue D
B.5. Differences between Issue D and Issue E
B.6. Differences between Issue E and Issue F
B.7. Differences between Issue F and Issue G

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Revision History
Revision A04 November 2011First release for r0p0
Revision B16 April 2012First release for r1p0
Revision C27 September 2012First release for r2p0
Revision D14 December 2012First release for r2p1
Revision E28 June 2013First release for r3p0
Revision F26 September 2013First release for r3p1
Revision G16 March 2015First release for r3p2
Copyright © 2011-2013, 2015 ARM. All rights reserved.ARM DDI 0480G