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The processor features and benefits are:
tight integration of system peripherals reduces area and development costs
Thumb instruction set combines high code density with 32-bit performance
support for single-cycle I/O access
power control optimization of system components
integrated sleep modes for low power consumption
fast code execution permits slower processor clock or increases sleep mode time
optimized code fetching for reduced flash and ROM power consumption
hardware multiplier
deterministic, high-performance interrupt handling for time-critical applications
deterministic instruction cycle timing
support for system level debug authentication
Serial Wire Debug reduces the number of pins required for debugging
support for optional instruction trace.
For information about Cortex-M0+ architectural compliance, see the Architecture and protocol information.