Cortex-M0+ Technical Reference ManualRevision: r0p0
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5.2. NVIC register summary

Table 5.1 shows the NVIC registers. Each of these registers is 32 bits wide.

Table 5.1. NVIC registers

NameDescription
NVIC_ISERInterrupt Set-Enable Register
NVIC_ICERInterrupt Clear-Enable Register
NVIC_ISPRInterrupt Set-Pending Register
NVIC_ICPRInterrupt Clear-Pending Register
NVIC_IPR0-NVIC_IPR7Interrupt Priority Registers

Note

See the ARMv6-M Architecture Reference Manual for more information about the NVIC registers and their addresses, access types, and reset values.

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