7.2. Debug register summary

Table 7.6 shows the debug registers. Each of these registers is 32 bits wide.

Table 7.6. Debug registers summary

NameDescription
DFSRDebug Fault Status Register in the ARMv6-M Architecture Reference Manual.
DHCSRDebug Halting Control and Status Register in the ARMv6-M Architecture Reference Manual.
DCRSRDebug Core Register Selector Register in the ARMv6-M Architecture Reference Manual.
DCRDRDebug Core Register Data Register in the ARMv6-M Architecture Reference Manual.
DEMCRDebug Exception and Monitor Control Register in the ARMv6-M Architecture Reference Manual.

Table 7.7 shows the BPU registers. Each of these registers is 32 bits wide.

Table 7.7. BPU register summary

NameDescription
BP_CTRLBreakpoint Control Register in the ARMv6-M Architecture Reference Manual.
BP_COMP0Breakpoint Comparator Registers in the ARMv6-M Architecture Reference Manual.
BP_COMP1
BP_COMP2
BP_COMP3

Table 7.8 shows the DWT registers. Each of these registers is 32 bits wide.

Table 7.8. DWT register summary

NameDescription
DWT_CTRLControl Register in the ARMv6-M Architecture Reference Manual.
DWT_PCSRProgram Counter Sample Register in the ARMv6-M Architecture Reference Manual.
DWT_COMP0Comparator Register in the ARMv6-M Architecture Reference Manual.
DWT_MASK0[a]Mask Register in the ARMv6-M Architecture Reference Manual.
DWT_FUNCTION0Function Register in the ARMv6-M Architecture Reference Manual.
DWT_COMP1Comparator Register in the ARMv6-M Architecture Reference Manual.
DWT_MASK1[a]Mask Register in the ARMv6-M Architecture Reference Manual.
DWT_FUNCTION1Function Register in the ARMv6-M Architecture Reference Manual.

[a] Supports masking up to 2GB.


See the ARMv6-M Architecture Reference Manual for more information about the debug registers and their addresses, access types, and reset values.

Note

Software cannot access the debug registers.

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